351 lines
7.6 KiB
ArmAsm
351 lines
7.6 KiB
ArmAsm
/* $NetBSD: locore.S,v 1.1 2001/07/28 15:08:11 chris Exp $ */
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/*
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* Copyright (C) 1994-1997 Mark Brinicombe
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* Copyright (C) 1994 Brini
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of Brini may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "opt_ipkdb.h"
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#include "assym.h"
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#include <sys/syscall.h>
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#include <sys/errno.h>
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#include <machine/asm.h>
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#include <machine/cpu.h>
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#include <machine/frame.h>
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#include <machine/param.h>
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/* What size should this really be ? It is only used by init_arm() */
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#define INIT_ARM_STACK_SIZE 2048
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/*
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* This is for kvm_mkdb, and should be the address of the beginning
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* of the kernel text segment (not necessarily the same as kernbase).
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*/
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#ifndef netwinder
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ENTRY_NP(kernel_text)
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#endif
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ASENTRY_NP(start)
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add r1, pc, #(Lstart - . - 8)
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ldmia r1, {r1, r2, sp} /* Set initial stack and */
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sub r2, r2, r1 /* get zero init data */
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mov r3, #0
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L1:
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str r3, [r1], #0x0004 /* Zero the bss */
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subs r2, r2, #4
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bgt L1
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mov fp, #0x00000000 /* trace back starts here */
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bl _C_LABEL(initarm) /* Off we go */
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/* init arm will return the new stack pointer. */
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mov sp, r0
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mov fp, #0x00000000 /* trace back starts here */
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mov ip, sp
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stmfd sp!, {fp, ip, lr, pc}
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sub fp, ip, #4
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/* Setup an initial trap frame for start_init to use */
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PUSHFRAME
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mov r0, sp /* parameter to main is trap frame */
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bl _C_LABEL(main) /* Lets light the flame and start her up */
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PULLFRAME /* Pull the trap frame, now valid */
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movs pc, lr /* Exit to user process */
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/* Never gets here */
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b .
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Lstart:
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.word _edata
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.word _end
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.word svcstk + INIT_ARM_STACK_SIZE
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.bss
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svcstk:
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.space INIT_ARM_STACK_SIZE
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/*
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* Instructions to copy to the bottom of zero page
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* These are the entry point to the system exception routines
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*/
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.text
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.align 0
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.global _C_LABEL(page0), _C_LABEL(page0_end)
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_C_LABEL(page0):
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ldr pc, [pc, #Lreset - . - 8]
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ldr pc, [pc, #Lundefined - . - 8]
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ldr pc, [pc, #Lswi - . - 8]
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ldr pc, [pc, #Labortpre - . - 8]
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ldr pc, [pc, #Labortdata - . - 8]
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ldr pc, [pc, #Laddrexc - . - 8]
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ldr pc, [pc, #Lirq - . - 8]
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ldr pc, [pc, #Lfiq - . - 8]
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Lreset:
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.word reset_entry
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Lundefined:
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.word undefined_entry
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Lswi:
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.word swi_entry
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Labortpre:
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.word prefetch_abort_entry
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Labortdata:
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.word data_abort_entry
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Laddrexc:
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.word addrexc
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Lirq:
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.word irq_entry
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Lfiq:
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.word fiq
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_C_LABEL(page0_end) = .
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/* vector 0x00000000 - RESET */
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ASENTRY_NP(reset_entry)
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PUSHFRAME
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mov r0, sp /* Pass the frame to function */
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b _C_LABEL(resethandler) /* It's a branch throught zero ! */
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/* vector 0x00000008 - ADDRESS EXCEPTION */
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ASENTRY_NP(addrexc)
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mrs r1, cpsr_all
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mrs r2, spsr_all
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mov r3, lr
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add r0, pc, #Laddrexcmsg - . - 8
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bl _C_LABEL(printf)
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b data_abort_entry
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Laddrexcmsg:
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.asciz "address exception CPSR=%08x SPSR=%08x lr=%08x\n"
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.align 0
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/* vector 0x0000001C - FIQ */
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ASENTRY_NP(fiq)
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ldr r0, Lfiqmsg
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b _C_LABEL(panic)
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Lfiqmsg:
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.asciz "fiq"
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.align 0
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#ifndef OFW
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/* OFW based systems will used OF_boot() */
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Lcpufuncs:
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.word _C_LABEL(cpufuncs)
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ENTRY_NP(cpu_reset)
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mrs r2, cpsr_all
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bic r2, r2, #(PSR_MODE)
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orr r2, r2, #(PSR_SVC32_MODE)
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orr r2, r2, #(I32_bit | F32_bit)
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msr cpsr_all, r2
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ldr r4, Lcpu_reset_address
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ldr r4, [r4]
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ldr r0, Lcpufuncs
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add lr, pc, #Lboot_cache_purged - . - 8
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ldr pc, [r0, #CF_CACHE_PURGE_ID]
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Lboot_cache_purged:
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/*
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* Load the cpu_reset_needs_v4_MMU_disable flag to determine if it's
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* necessary.
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*/
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ldr r1, Lcpu_reset_needs_v4_MMU_disable
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ldr r1, [r1]
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cmp r1, #0
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/*
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* MMU & IDC off, 32 bit program & data space
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* Hurl ourselves into the ROM
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*/
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mov r0, #(CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE)
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mcr 15, 0, r0, c1, c0, 0
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mcrne 15, 0, r0, c8, c7, 0 /* only when v4 MMU disable is asked for */
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mov pc, r4
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/*
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* _cpu_reset_address contains the address to branch to, to complete
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* the cpu reset after turning the MMU off
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* This variable is provided by the hardware specific code
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*/
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Lcpu_reset_address:
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.word _C_LABEL(cpu_reset_address)
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/*
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* cpu_reset_needs_v4_MMU_disable contains a flag that signals if the
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* v4 MMU disable instruction needs executing... it is an illegal instruction
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* on f.e. ARM6/7 that locks up the computer in an endless illegal
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* instruction / data-abort / reset loop.
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*/
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Lcpu_reset_needs_v4_MMU_disable:
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.word _C_LABEL(cpu_reset_needs_v4_MMU_disable)
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#endif /* OFW */
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#ifdef IPKDB
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#if 0
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/*
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* ipkdbfbyte and ipkdbsbyte are now in ipkdb_glue.c and do not tweak
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* the abort handler anymore
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*/
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ENTRY_NP(ipkdbfbyte)
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ldr ip, abortp
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ldr r2, [ip]
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add r3, pc, #ipkdbfault - . - 8
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str r3, [ip]
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ldrb r0, [r0]
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str r2, [ip]
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mov pc, lr
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ENTRY_NP(ipkdbsbyte)
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ldr ip, abortp
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ldr r2, [ip]
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add r3, pc, #ipkdbfault - . - 8
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str r3, [ip]
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strb r1, [r0]
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sub r0, r0, r0
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str r2, [ip]
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mov pc, lr
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abortp:
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.word Labortdata - _C_LABEL(page0)
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ipkdbfault:
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mov r0, #0xd3
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msr cpsr_all, r0
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mvn r0, #0 /* mov r0, #-1 */
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str r2, [ip]
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mov pc, lr
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#endif
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/*
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* Execute(inst, psr, args, sp)
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*
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* Execute INSTruction with PSR and ARGS[0] - ARGS[3] making
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* available stack at SP for next undefined instruction trap.
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*
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* Move the instruction onto the stack and jump to it.
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*/
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ENTRY_NP(Execute)
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mov ip, sp
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stmfd sp!, {r2, r4-r7, fp, ip, lr, pc}
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sub fp, ip, #4
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mov ip, r3
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ldr r7, return
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stmfd sp!, {r0, r7}
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add r7, pc, #LExec - . - 8
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mov r5, r1
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mrs r4, cpsr_all
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ldmia r2, {r0-r3}
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mov r6, sp
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mov sp, ip
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msr cpsr_all, r5
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mov pc, r6
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LExec:
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mrs r5, cpsr_all
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/* XXX Cannot switch thus easily back from user mode */
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msr cpsr_all, r4
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add sp, r6, #8
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ldmfd sp!, {r6}
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stmia r6, {r0-r3}
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mov r0, r5
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ldmdb fp, {r4-r7, fp, sp, pc}
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return:
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mov pc, r7
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#endif
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/*
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* setjump + longjmp
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*/
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ENTRY(setjmp)
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stmia r0, {r4-r14}
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mov r0, #0x00000000
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mov pc, lr
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ENTRY(longjmp)
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ldmia r0, {r4-r14}
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mov r0, #0x00000001
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mov pc, lr
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.data
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.global _C_LABEL(esym)
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_C_LABEL(esym): .word _C_LABEL(end)
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ENTRY_NP(abort)
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b _C_LABEL(abort)
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/*
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* Atomic bit set and clear functions
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*/
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ENTRY(atomic_set_bit)
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mrs r2, cpsr_all
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orr r3, r2, #(I32_bit)
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msr cpsr_all, r3
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ldr r3, [r0]
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orr r3, r3, r1
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str r3, [r0]
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msr cpsr_all, r2
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mov pc, lr
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ENTRY(atomic_clear_bit)
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mrs r2, cpsr_all
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orr r3, r2, #(I32_bit)
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msr cpsr_all, r3
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ldr r3, [r0]
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bic r3, r3, r1
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str r3, [r0]
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msr cpsr_all, r2
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mov pc, lr
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/* End of locore.S */
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