670f0a07d9
longer a forced correspondence between bit numbers in an interrupt register and bit numbers in an spl mask. This will avoid conflicts between various interrupt registers in the same system. Instead, bits in the spl mask are allocated on a first come, first served basis by devices which can interrupt. The new hp700_intr_ipending_new takes care of reading all interrupt request registers that need servicing, and mapping the bits set in those registers to new bits set in ipending. This whole mechanism is in and works. A later commit will see the I/O subsystems fixing which bits in their interrupt registers are connected to which devices, largely removing irq information from kernel configuration files. There will also be a cosmetic fix to show which spl bit corresponds to a device.
199 lines
5.8 KiB
C
199 lines
5.8 KiB
C
/* $NetBSD: intr.h,v 1.2 2002/08/14 16:18:13 fredette Exp $ */
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/*-
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* Copyright (c) 1998, 2001, 2002 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Charles M. Hannum, and by Jason R. Thorpe, and by Matthew Fredette.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _HP700_INTR_H_
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#define _HP700_INTR_H_
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#include <machine/psl.h>
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/* Interrupt priority `levels'. */
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#define IPL_NONE 9 /* nothing */
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#define IPL_SOFTCLOCK 8 /* timeouts */
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#define IPL_SOFTNET 7 /* protocol stacks */
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#define IPL_BIO 6 /* block I/O */
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#define IPL_NET 5 /* network */
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#define IPL_SOFTSERIAL 4 /* serial */
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#define IPL_TTY 3 /* terminal */
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#define IPL_IMP 3 /* memory allocation */
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#define IPL_AUDIO 2 /* audio */
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#define IPL_CLOCK 1 /* clock */
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#define IPL_HIGH 1 /* everything */
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#define IPL_SERIAL 0 /* serial */
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#define NIPL 10
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/* Interrupt sharing types. */
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#define IST_NONE 0 /* none */
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#define IST_PULSE 1 /* pulsed */
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#define IST_EDGE 2 /* edge-triggered */
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#define IST_LEVEL 3 /* level-triggered */
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#ifndef _LOCORE
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/* The priority level masks. */
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extern int imask[NIPL];
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/* The current priority level. */
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extern volatile int cpl;
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/* The asynchronous system trap flag. */
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extern volatile int astpending;
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/* The softnet mask. */
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extern int softnetmask;
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/*
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* Add a mask to cpl, and return the old value of cpl.
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*/
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static __inline int splraise __P((int));
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static __inline int
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splraise(ncpl)
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register int ncpl;
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{
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register int ocpl = cpl;
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cpl = ocpl | ncpl;
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return (ocpl);
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}
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/* spllower() is in locore.S */
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void spllower __P((int));
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/*
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* Hardware interrupt masks
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*/
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#define splbio() splraise(imask[IPL_BIO])
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#define splnet() splraise(imask[IPL_NET])
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#define spltty() splraise(imask[IPL_TTY])
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#define splaudio() splraise(imask[IPL_AUDIO])
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#define splclock() splraise(imask[IPL_CLOCK])
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#define splstatclock() splclock()
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#define splserial() splraise(imask[IPL_SERIAL])
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#define spllpt() spltty()
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/*
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* Software interrupt masks
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*
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* NOTE: splsoftclock() is used by hardclock() to lower the priority from
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* clock to softclock before it calls softclock().
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*/
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#define spllowersoftclock() spllower(imask[IPL_SOFTCLOCK])
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#define splsoftclock() splraise(imask[IPL_SOFTCLOCK])
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#define splsoftnet() splraise(imask[IPL_SOFTNET])
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#define splsoftserial() splraise(imask[IPL_SOFTSERIAL])
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/*
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* Miscellaneous
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*/
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#define splvm() splraise(imask[IPL_IMP])
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#define splhigh() splraise(imask[IPL_HIGH])
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#define splsched() splhigh()
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#define spllock() splhigh()
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#define spl0() spllower(0)
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#define splx(x) spllower(x)
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#define setsoftast() (astpending = 1)
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#define setsoftnet() hp700_intr_schedule(softnetmask)
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#endif /* !_LOCORE */
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/*
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* Generic software interrupt support.
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*/
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#define HP700_SOFTINTR_SOFTCLOCK 0
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#define HP700_SOFTINTR_SOFTNET 1
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#define HP700_SOFTINTR_SOFTSERIAL 2
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#define HP700_NSOFTINTR 3
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#ifndef _LOCORE
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#include <sys/queue.h>
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#include <sys/device.h>
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struct hp700_soft_intrhand {
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TAILQ_ENTRY(hp700_soft_intrhand)
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sih_q;
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struct hp700_soft_intr *sih_intrhead;
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void (*sih_fn)(void *);
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void *sih_arg;
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int sih_pending;
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};
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struct hp700_soft_intr {
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TAILQ_HEAD(, hp700_soft_intrhand)
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softintr_q;
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int softintr_ssir;
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};
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#define hp700_softintr_lock(si, s) \
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do { \
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(s) = splhigh(); \
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} while (/*CONSTCOND*/ 0)
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#define hp700_softintr_unlock(si, s) \
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do { \
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splx((s)); \
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} while (/*CONSTCOND*/ 0)
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void *softintr_establish __P((int, void (*)(void *), void *));
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void softintr_disestablish __P((void *));
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void softintr_bootstrap __P((void));
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void softintr_init __P((void));
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int softintr_dispatch __P((void *));
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#define softintr_schedule(arg) \
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do { \
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struct hp700_soft_intrhand *__sih = (arg); \
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struct hp700_soft_intr *__si = __sih->sih_intrhead; \
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int __s; \
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\
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hp700_softintr_lock(__si, __s); \
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if (__sih->sih_pending == 0) { \
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TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q); \
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__sih->sih_pending = 1; \
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hp700_intr_schedule(__si->softintr_ssir); \
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} \
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hp700_softintr_unlock(__si, __s); \
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} while (/*CONSTCOND*/ 0)
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void hp700_intr_schedule __P((int));
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#endif /* _LOCORE */
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#endif /* !_HP700_INTR_H_ */
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