eb20bbc780
that is priority is rasied. Add a new spllowersoftclock() to provide the atomic drop-to-softclock semantics that the old splsoftclock() provided, and update calls accordingly. This fixes a problem with using the "rnd" pseudo-device from within interrupt context to extract random data (e.g. from within the softnet interrupt) where doing so would incorrectly unblock interrupts (causing all sorts of lossage). XXX 4 platforms do not have priority-raising capability: newsmips, sparc, XXX sparc64, and VAX. This platforms still have this bug until their XXX spl*() functions are fixed.
112 lines
3.9 KiB
C
112 lines
3.9 KiB
C
/* $NetBSD: psl.h,v 1.15 1999/08/05 18:08:14 thorpej Exp $ */
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/*-
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* Copyright (c) 1996 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Gordon W. Ross.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SUN3_PSL_H_
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#define _SUN3_PSL_H_
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#include <m68k/psl.h>
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/* Could define this in the common <m68k/psl.h> instead. */
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#if defined(_KERNEL) && !defined(_LOCORE)
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/*
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* Define inline functions for PSL manipulation.
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* These are as close to macros as one can get.
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* When not optimizing gcc will call the locore.s
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* functions by the same names, so breakpoints on
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* these functions will work normally, etc.
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* (See the GCC extensions info document.)
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*/
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static __inline int _getsr __P((void));
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/* Get current sr value. */
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static __inline int
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_getsr(void)
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{
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register int rv;
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__asm __volatile ("clrl %0; movew sr,%0" : "&=d" (rv));
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return (rv);
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}
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/*
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* The rest of this is sun3 specific, because other ports may
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* need to do special things in spl0() (i.e. simulate SIR).
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* Suns have a REAL interrupt register, so spl0() and splx(s)
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* have no need to check for any simulated interrupts, etc.
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*/
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#define spl0() _spl0() /* we have real software interrupts */
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#define splx(x) _spl(x)
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/* IPL used by soft interrupts: netintr(), softclock() */
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#define spllowersoftclock() spl1()
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#define splsoftclock() splraise1()
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#define splsoftnet() splraise1()
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/* Highest block device (strategy) IPL. */
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#define splbio() splraise2()
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/* Highest network interface IPL. */
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#define splnet() splraise3()
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/* Highest tty device IPL. */
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#define spltty() splraise4()
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/*
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* Requirement: imp >= (highest network, tty, or disk IPL)
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* This is used mostly in the VM code. (Why not splvm?)
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* Note that the VM code runs at spl7 during kernel
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* initialization, and later at spl0, so we have to
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* use splraise to avoid enabling interrupts early.
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*/
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#define splimp() _splraise(PSL_S|PSL_IPL4)
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/* Intersil clock hardware interrupts (hard-wired at 5) */
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#define splclock() splraise5()
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#define splstatclock() splclock()
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/* Block out all interrupts (except NMI of course). */
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#define splhigh() spl7()
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#define splsched() spl7()
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#endif /* KERNEL && !_LOCORE */
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#endif /* _SUN3_PSL_H_ */
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