c907dcc22c
- Implement pioc device driver that handles the memory mapped serial,
parallel, floppy and IDE interfaces.
- Provide child attachments to the generic drivers for serial,
parallel and IDE.
125 lines
4.7 KiB
C
125 lines
4.7 KiB
C
/* $NetBSD: piocreg.h,v 1.1 1997/10/14 19:57:44 mark Exp $ */
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/*
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* Copyright (c) 1997 Mark Brinicombe.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Peripheral I/O controller registers
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*/
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/*
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*
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*/
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#define PIOC_SIZE (0x1000 + 0x2000) /* XXX */
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/*
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* I/O registers for managing PIOC configuration
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*/
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#define PIOC_CM_SELECT_REG 0x3f0
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#define PIOC_CM_DATA_REG 0x3f1
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/*
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* Bytes to write to the select register to switch in and out for config mode
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*/
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#define PIOC_CM_ENTER_665 0x55 /* SMC FDC37GT665 */
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#define PIOC_CM_ENTER_666 0x44 /* SMC FDC37GT666 */
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#define PIOC_CM_EXIT 0xaa
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/*
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* Configuration register selection codes
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*/
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#define PIOC_CM_CR0 0x0 /* IDE and floppy setup */
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#define PIOC_WDC_ENABLE 0x01 /* wdc enable */
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#define PIOC_FDC_ENABLE 0x10 /* fdc enable */
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#define PIOC_CM_CR1 0x1 /* parallel and serial setup */
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#define PIOC_LPT_ADDR_MASK 0x03 /* lpt address mask */
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#define PIOC_LPT_ADDR_DISABLE 0x00 /* lpt disabled */
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#define PIOC_LPT_ADDR_1 0x01 /* lpt address 1 */
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#define PIOC_LPT_ADDR_2 0x02 /* lpt address 2 */
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#define PIOC_LPT_ADDR_3 0x03 /* lpt address 3 */
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#define PIOC_CM_CR2 0x2 /* serial setup */
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#define PIOC_UART1_ADDR_MASK 0x03 /* uart1 address mask */
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#define PIOC_UART1_ADDR_COM1 0x00 /* uart1 address com1 */
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#define PIOC_UART1_ADDR_COM2 0x01 /* uart1 address com2 */
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#define PIOC_UART1_ADDR_COM3 0x02 /* uart1 address com3 */
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#define PIOC_UART1_ADDR_COM4 0x03 /* uart1 address com4 */
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#define PIOC_UART1_ENABLE 0x04 /* uart1 enable */
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#define PIOC_UART2_ADDR_MASK 0x30 /* uart2 address mask */
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#define PIOC_UART2_ADDR_COM1 0x00 /* uart2 address com1 */
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#define PIOC_UART2_ADDR_COM2 0x10 /* uart2 address com2 */
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#define PIOC_UART2_ADDR_COM3 0x20 /* uart2 address com3 */
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#define PIOC_UART2_ADDR_COM4 0x30 /* uart2 address com4 */
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#define PIOC_UART2_ENABLE 0x40 /* uart2 enable */
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#define PIOC_CM_CR3 0x3 /* parallel setup */
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#define PIOC_CM_CR4 0x4 /* parallel and serial extended setup */
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#define PIOC_CM_CR5 0x5 /* floppy & IDE extended setup */
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#define PIOC_FDC_SECONDARY 0x01 /* fdc secondary address enable */
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#define PIOC_WDC_SECONDARY 0x02 /* wdc secondary address enable */
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#define PIOC_CM_CR6 0x6 /* floppy drive types */
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#define PIOC_CM_CR7 0x7 /* media ID & boot drive */
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#define PIOC_CM_CR8 0x8 /* PIOC address low */
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#define PIOC_CM_CR9 0x9 /* PIOC address high */
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#define PIOC_CM_CRA 0xa /* ECP FIFO threshold */
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#define PIOC_CM_CRB 0xb /* reserved */
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#define PIOC_CM_CRC 0xc /* reserved */
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#define PIOC_CM_CRD 0xd /* PIOC ID */
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#define PIOC_CM_CRE 0xe /* PIOC revision */
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#define PIOC_CM_CRF 0xf /* reserve for testing */
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#define PIOC_CM_REGS 0x10 /* number of registers */
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/*
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* PIOC ID values
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*/
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#define PIOC_CM_ID_665 0x65
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#define PIOC_CM_ID_666 0x66
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/*
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* PIOC offsets
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*/
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#define PIOC_FDC_PRIMARY_OFFSET 0x3f0
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#define PIOC_FDC_SECONDARY_OFFSET 0x370
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#define PIOC_WDC_PRIMARY_OFFSET 0x1f0
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#define PIOC_WDC_SECONDARY_OFFSET 0x170
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#define PIOC_LPT1_OFFSET 0x3bc
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#define PIOC_LPT2_OFFSET 0x378
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#define PIOC_LPT3_OFFSET 0x278
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#define PIOC_COM1_OFFSET 0x3f8
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#define PIOC_COM2_OFFSET 0x2f8
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#define PIOC_COM3_OFFSET 0x338
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#define PIOC_COM4_OFFSET 0x238
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/* End of piocreg.h */
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