105 lines
3.7 KiB
C
105 lines
3.7 KiB
C
/* $NetBSD: pciide_cmd_reg.h,v 1.17 2009/10/19 18:41:15 bouyer Exp $ */
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/*
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* Copyright (c) 1998 Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/*
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* Registers definitions for CMD Technologies's PCI 064x IDE controllers.
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* Available from http://www.cmd.com/
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*/
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/* Interesting revision of the 0646 */
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#define CMD0646U2_REV 0x05
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#define CMD0646U_REV 0x03
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/* Configuration (RO) */
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#define CMD_CONF 0x50
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#define CMD_CONF_REV_MASK 0x03 /* 0640/3/6 only */
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#define CMD_CONF_DRV0_INTR 0x04
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#define CMD_CONF_DEVID 0x18 /* 0640/3/6 only */
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#define CMD_CONF_VESAPRT 0x20 /* 0640/3/6 only */
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#define CMD_CONF_DSA1 0x40
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#define CMD_CONF_DSA0 0x80 /* 0640/3/6 only */
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/* Control register (RW) */
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#define CMD_CTRL 0x51
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#define CMD_CTRL_HR_FIFO 0x01 /* 0640/3/6 only */
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#define CMD_CTRL_HW_FIFO 0x02 /* 0640/3/6 only */
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#define CMD_CTRL_DEVSEL 0x04
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#define CMD_CTRL_2PORT 0x08
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#define CMD_CTRL_PAR 0x10 /* 0640/3/6 only */
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#define CMD_CTRL_HW_HLD 0x20 /* 0640/3/6 only */
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#define CMD_CTRL_DRV0_RAHEAD 0x40
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#define CMD_CTRL_DRV1_RAHEAD 0x80
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/*
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* data read/write timing registers . 0640 uses the same for drive 0 and 1
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* on the secondary channel
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*/
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#define CMD_DATA_TIM(chan, drive) \
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(((chan) == 0) ? \
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((drive) == 0) ? 0x54: 0x56 \
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: \
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((drive) == 0) ? 0x58 : 0x5b)
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/* secondary channel status and addr timings */
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#define CMD_ARTTIM23 0x57
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#define CMD_ARTTIM23_IRQ 0x10
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#define CMD_ARTTIM23_RHAEAD(d) ((0x4) << (d))
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/* DMA master read mode select */
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#define CMD_DMA_MODE 0x71
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#define CMD_DMA_MASK 0x03
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#define CMD_DMA 0x00
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#define CMD_DMA_MULTIPLE 0x01
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#define CMD_DMA_LINE 0x03
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/* the followings bits are only for 0646U/646U2/648/649 */
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#define CMD_DMA_IRQ(chan) (0x4 << (chan))
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#define CMD_DMA_IRQ_DIS(chan) (0x10 << (chan))
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#define CMD_DMA_RST 0x40
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/* the followings are only for 0646U/646U2/648/649 */
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/* busmaster control/status register */
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#define CMD_BICSR 0x79
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#define CMD_BICSR_80(chan) (0x01 << (chan))
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/* Ultra/DMA timings reg */
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#define CMD_UDMATIM(channel) (0x73 + (8 * (channel)))
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#define CMD_UDMATIM_UDMA(drive) (0x01 << (drive))
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#define CMD_UDMATIM_UDMA33(drive) (0x04 << (drive))
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#define CMD_UDMATIM_TIM_MASK 0x3
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#define CMD_UDMATIM_TIM_OFF(drive) (4 + ((drive) * 2))
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static const int8_t cmd0646_9_tim_udma[] __unused =
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{0x03, 0x02, 0x01, 0x02, 0x01, 0x00};
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/*
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* timings values for the 0643/6/8/9
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* for all dma_mode we have to have
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* DMA_timings(dma_mode) >= PIO_timings(dma_mode + 2)
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*/
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static const int8_t cmd0643_9_data_tim_pio[] __unused =
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{0xA9, 0x57, 0x44, 0x32, 0x3F};
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static const int8_t cmd0643_9_data_tim_dma[] __unused =
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{0x87, 0x32, 0x3F};
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