618 lines
24 KiB
C
618 lines
24 KiB
C
/* $NetBSD: if_casreg.h,v 1.1 2010/01/07 09:19:55 jdc Exp $ */
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/* $OpenBSD: if_casreg.h,v 1.10 2008/05/31 22:49:03 kettenis Exp $ */
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/*
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*
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* Copyright (C) 2007 Mark Kettenis.
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* Copyright (C) 2001 Eduardo Horvath.
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* All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#ifndef _IF_CASREG_H
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#define _IF_CASREG_H
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/*
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* Register definitions for Sun Cassini ethernet controllers.
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*/
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/*
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* First bank: these registers live at the start of the PCI mapping.
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*/
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#define CAS_SEB_STATE 0x0000 /* SEB state reg, R/O */
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#define CAS_CONFIG 0x0004 /* config reg */
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#define CAS_STATUS 0x000c /* status reg */
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/* Note: Reading the status reg clears bits 0-6 */
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#define CAS_INTMASK 0x0010
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#define CAS_INTACK 0x0014 /* Interrupt acknowledge, W/O */
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#define CAS_STATUS_ALIAS 0x001c
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/* Note: Same as CAS_STATUS but reading it does not clear bits. */
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#define CAS_ERROR_STATUS 0x1000 /* PCI error status R/C */
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#define CAS_ERROR_MASK 0x0004
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#define CAS_BIF_CONFIG 0x0008 /* BIF config reg */
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#define CAS_BIF_DIAG 0x000c
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#define CAS_RESET 0x1010 /* Software reset register */
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/* Bits in CAS_SEB register */
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#define CAS_SEB_ARB 0x000000002 /* Arbitration status */
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#define CAS_SEB_RXWON 0x000000004
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/* Bits in CAS_CONFIG register */
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#define CAS_CONFIG_BURST_64 0x000000000 /* 0->infinity, 1->64KB */
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#define CAS_CONFIG_BURST_INF 0x000000001 /* 0->infinity, 1->64KB */
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#define CAS_CONFIG_TXDMA_LIMIT 0x00000003e
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#define CAS_CONFIG_RXDMA_LIMIT 0x0000007c0
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#define CAS_CONFIG_TXDMA_LIMIT_SHIFT 1
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#define CAS_CONFIG_RXDMA_LIMIT_SHIFT 6
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/* Top part of CAS_STATUS has TX completion information */
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#define CAS_STATUS_TX_COMPL 0xfff800000 /* TX completion reg. */
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/*
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* Interrupt bits, for both the CAS_STATUS and CAS_INTMASK regs.
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* Bits 0-6 auto-clear when read.
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*/
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#define CAS_INTR_TX_INTME 0x000000001 /* Frame w/INTME bit set sent */
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#define CAS_INTR_TX_EMPTY 0x000000002 /* TX ring empty */
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#define CAS_INTR_TX_DONE 0x000000004 /* TX complete */
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#define CAS_INTR_TX_TAG_ERR 0x000000008
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#define CAS_INTR_RX_DONE 0x000000010 /* Got a packet */
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#define CAS_INTR_RX_NOBUF 0x000000020
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#define CAS_INTR_RX_TAG_ERR 0x000000040
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#define CAS_INTR_RX_COMP_FULL 0x000000080
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#define CAS_INTR_PCS 0x000002000 /* Physical Code Sub-layer */
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#define CAS_INTR_TX_MAC 0x000004000
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#define CAS_INTR_RX_MAC 0x000008000
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#define CAS_INTR_MAC_CONTROL 0x000010000 /* MAC control interrupt */
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#define CAS_INTR_MIF 0x000020000
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#define CAS_INTR_BERR 0x000040000 /* Bus error interrupt */
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#define CAS_INTR_BITS "\020" \
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"\1INTME\2TXEMPTY\3TXDONE\4TX_TAG_ERR" \
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"\5RXDONE\6RXNOBUF\7RX_TAG_ERR" \
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"\10RX_COMP_FULL" \
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"\16PCS\17TXMAC\20RXMAC" \
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"\21MACCONTROL\22MIF\23BERR"
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/* CAS_ERROR_STATUS and CAS_ERROR_MASK PCI error bits */
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#define CAS_ERROR_STAT_BADACK 0x000000001 /* No ACK64# */
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#define CAS_ERROR_STAT_DTRTO 0x000000002 /* Delayed xaction timeout */
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#define CAS_ERROR_STAT_OTHERS 0x000000004
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/* CAS_BIF_CONFIG register bits */
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#define CAS_BIF_CONFIG_SLOWCLK 0x000000001 /* Parity error timing */
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#define CAS_BIF_CONFIG_HOST_64 0x000000002 /* 64-bit host */
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#define CAS_BIF_CONFIG_B64D_DIS 0x000000004 /* no 64-bit data cycle */
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#define CAS_BIF_CONFIG_M66EN 0x000000008
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/* CAS_RESET register bits -- TX and RX self clear when complete. */
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#define CAS_RESET_TX 0x000000001 /* Reset TX half */
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#define CAS_RESET_RX 0x000000002 /* Reset RX half */
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#define CAS_RESET_RSTOUT 0x000000004 /* Force PCI RSTOUT# */
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#define CAS_RESET_BLOCK_PCS 0x00000008 /* Block PCS reset */
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/* TX DMA registers */
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#define CAS_TX_CONFIG 0x2004
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#define CAS_TX_FIFO_WR_PTR 0x2014 /* FIFO write pointer */
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#define CAS_TX_FIFO_SDWR_PTR 0x2018 /* FIFO shadow write pointer */
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#define CAS_TX_FIFO_RD_PTR 0x201c /* FIFO read pointer */
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#define CAS_TX_FIFO_SDRD_PTR 0x2020 /* FIFO shadow read pointer */
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#define CAS_TX_FIFO_PKT_CNT 0x2024 /* FIFO packet counter */
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#define CAS_TX_STATE_MACHINE 0x2028 /* ETX state machine reg */
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#define CAS_TX_DATA_PTR 0x2030 /* ETX state machine reg (64-bit)*/
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#define CAS_TX_KICK1 0x2038 /* Write last valid desc + 1 */
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#define CAS_TX_KICK2 0x203c
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#define CAS_TX_KICK3 0x2040
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#define CAS_TX_KICK4 0x2044
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#define CAS_TX_COMPLETION1 0x2048
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#define CAS_TX_COMPLETION2 0x204c
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#define CAS_TX_COMPLETION3 0x2050
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#define CAS_TX_COMPLETION4 0x2054
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#define CAS_TX_RING_PTR_LO1 0x2060
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#define CAS_TX_RING_PTR_HI1 0x2064
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#define CAS_TX_RING_PTR_LO2 0x2068
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#define CAS_TX_RING_PTR_HI2 0x206c
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#define CAS_TX_RING_PTR_LO3 0x2070
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#define CAS_TX_RING_PTR_HI3 0x2074
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#define CAS_TX_RING_PTR_LO4 0x2078
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#define CAS_TX_RING_PTR_HI4 0x207c
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#define CAS_TX_MAXBURST1 0x2080
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#define CAS_TX_MAXBURST2 0x2084
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#define CAS_TX_MAXBURST3 0x2088
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#define CAS_TX_MAXBURST4 0x208c
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#define CAS_TX_KICK CAS_TX_KICK3
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#define CAS_TX_COMPLETION CAS_TX_COMPLETION3
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#define CAS_TX_RING_PTR_LO CAS_TX_RING_PTR_LO3
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#define CAS_TX_RING_PTR_HI CAS_TX_RING_PTR_HI3
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#define CAS_TX_FIFO_ADDRESS 0x2104
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#define CAS_TX_FIFO_TAG 0x2108
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#define CAS_TX_FIFO_DATA_LO 0x210c
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#define CAS_TX_FIFO_DATA_HI_T1 0x2110
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#define CAS_TX_FIFO_DATA_HI_T0 0x2114
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#define CAS_TX_FIFO_SIZE 0x2118
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#define CAS_TX_DEBUG 0x3028
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/* CAS_TX_CONFIG register bits. */
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#define CAS_TX_CONFIG_TXDMA_EN 0x00000001 /* TX DMA enable */
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#define CAS_TX_CONFIG_TXRING_SZ 0x0000003c /* TX ring size */
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#define CAS_TX_CONFIG_PACED 0x00100000 /* TX_all_int modifier */
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#define CAS_RING_SZ_32 0 /* 32 descriptors */
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#define CAS_RING_SZ_64 1
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#define CAS_RING_SZ_128 2
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#define CAS_RING_SZ_256 3
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#define CAS_RING_SZ_512 4
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#define CAS_RING_SZ_1024 5
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#define CAS_RING_SZ_2048 6
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#define CAS_RING_SZ_4096 7
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#define CAS_RING_SZ_8192 8
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/* CAS_TX_COMPLETION register bits */
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#define CAS_TX_COMPLETION_MASK 0x00001fff /* # of last descriptor */
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/* RX DMA registers */
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#define CAS_RX_CONFIG 0x4000
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#define CAS_RX_PAGE_SIZE 0x4004
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#define CAS_RX_FIFO_WR_PTR 0x4008 /* FIFO write pointer */
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#define CAS_RX_FIFO_RD_PTR 0x400c /* FIFO read pointer */
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#define CAS_RX_IPPFIFO_WR_PTR 0x4010 /* IPP FIFO write pointer */
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#define CAS_RX_IPPFIFO_RD_PTR 0x4014 /* IPP FIFO read pointer */
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#define CAS_RX_IPPFIFO_SDWR_PTR 0x4018 /* FIFO shadow write pointer */
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#define CAS_RX_DEBUG 0x401c /* Debug reg */
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#define CAS_RX_PAUSE_THRESH 0x4020
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#define CAS_RX_KICK 0x4024 /* Write last valid desc + 1 */
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#define CAS_RX_DRING_PTR_LO 0x4028
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#define CAS_RX_DRING_PTR_HI 0x402c
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#define CAS_RX_CRING_PTR_LO 0x4030
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#define CAS_RX_CRING_PTR_HI 0x4034
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#define CAS_RX_COMPLETION 0x4038 /* First pending desc */
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#define CAS_RX_COMP_HEAD 0x403c
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#define CAS_RX_COMP_TAIL 0x4040
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#define CAS_RX_BLANKING 0x4044 /* Interrupt blanking reg */
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#define CAS_RX_RED 0x404c /* Random Early Detection */
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#define CAS_RX_IPP_PKT_CNT 0x4054 /* IPP packet counter */
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#define CAS_RX_FIFO_ADDRESS 0x4080
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#define CAS_RX_FIFO_TAG 0x4084
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#define CAS_RX_FIFO_DATA_LO 0x4088
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#define CAS_RX_FIFO_DATA_HI_T0 0x408c
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#define CAS_RX_FIFO_DATA_HI_T1 0x4090
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/* The following registers only exist on Cassini+. */
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#define CAS_RX_DRING_PTR_LO2 0x4200
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#define CAS_RX_DRING_PTR_HI2 0x4204
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#define CAS_RX_CRING_PTR_LO2 0x4208
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#define CAS_RX_CRING_PTR_HI2 0x420c
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#define CAS_RX_CRING_PTR_LO3 0x4210
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#define CAS_RX_CRING_PTR_HI3 0x4214
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#define CAS_RX_CRING_PTR_LO4 0x4218
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#define CAS_RX_CRING_PTR_HI4 0x421c
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#define CAS_RX_KICK2 0x4220
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#define CAS_RX_COMPLETION2 0x4224
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#define CAS_RX_COMP_HEAD2 0x4228
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#define CAS_RX_COMP_TAIL2 0x422c
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#define CAS_RX_COMP_HEAD3 0x4230
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#define CAS_RX_COMP_TAIL3 0x4234
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#define CAS_RX_COMP_HEAD4 0x4238
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#define CAS_RX_COMP_TAIL4 0x423c
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/* CAS_RX_CONFIG register bits. */
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#define CAS_RX_CONFIG_RXDMA_EN 0x00000001 /* RX DMA enable */
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#define CAS_RX_CONFIG_RXDRNG_SZ 0x0000001e /* RX descriptor ring size */
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#define CAS_RX_CONFIG_RXCRNG_SZ 0x000001e0 /* RX completion ring size */
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#define CAS_RX_CONFIG_BATCH_DIS 0x00000200 /* desc batching disable */
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#define CAS_RX_CONFIG_FBOFF 0x00001c00 /* first byte offset */
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#define CAS_RX_CONFIG_RXDRNG_SZ_SHIFT 1
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#define CAS_RX_CONFIG_RXCRNG_SZ_SHIFT 5
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#define CAS_RX_CONFIG_FBOFF_SHFT 10
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#define CAS_RX_CONFIG_RXDRNG2_SZ_SHIFT 16 /* Cassini+ */
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/* CAS_RX_PAGE_SIZE register bits. */
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#define CAS_RX_PAGE_SIZE_SZ 0x00000003 /* Page size */
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#define CAS_RX_PAGE_SIZE_COUNT 0x00007800 /* MTU buffers per page */
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#define CAS_RX_PAGE_SIZE_STRIDE 0x18000000 /* MTU buffer separation */
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#define CAS_RX_PAGE_SIZE_FBOFF 0xc0000000 /* Firts byte offset */
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#define CAS_RX_PAGE_SIZE_COUNT_SHIFT 11
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#define CAS_RX_PAGE_SIZE_STRIDE_SHIFT 27
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#define CAS_RX_PAGE_SIZE_FBOFF_SHIFT 30
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/* CAS_RX_PAUSE_THRESH register bits -- sizes in multiples of 64 bytes */
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#define CAS_RX_PTH_XOFF_THRESH 0x000001ff
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#define CAS_RX_PTH_XON_THRESH 0x07fc0000
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/* CAS_RX_BLANKING register bits */
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#define CAS_RX_BLANKING_PACKETS 0x000001ff /* Delay intr for x packets */
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#define CAS_RX_BLANKING_TIME 0x03fc0000 /* Delay intr for x ticks */
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/* One tick is 1048 PCI clocks, or 16us at 66MHz */
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/* CAS_MAC registers */
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#define CAS_MAC_TXRESET 0x6000 /* Store 1, cleared when done */
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#define CAS_MAC_RXRESET 0x6004 /* ditto */
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#define CAS_MAC_SEND_PAUSE_CMD 0x6008
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#define CAS_MAC_TX_STATUS 0x6010
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#define CAS_MAC_RX_STATUS 0x6014
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#define CAS_MAC_CONTROL_STATUS 0x6018 /* MAC control status reg */
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#define CAS_MAC_TX_MASK 0x6020 /* TX MAC mask register */
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#define CAS_MAC_RX_MASK 0x6024
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#define CAS_MAC_CONTROL_MASK 0x6028
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#define CAS_MAC_TX_CONFIG 0x6030
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#define CAS_MAC_RX_CONFIG 0x6034
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#define CAS_MAC_CONTROL_CONFIG 0x6038
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#define CAS_MAC_XIF_CONFIG 0x603c
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#define CAS_MAC_IPG0 0x6040 /* inter packet gap 0 */
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#define CAS_MAC_IPG1 0x6044 /* inter packet gap 1 */
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#define CAS_MAC_IPG2 0x6048 /* inter packet gap 2 */
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#define CAS_MAC_SLOT_TIME 0x604c /* slot time, bits 0-7 */
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#define CAS_MAC_MAC_MIN_FRAME 0x6050
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#define CAS_MAC_MAC_MAX_FRAME 0x6054
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#define CAS_MAC_PREAMBLE_LEN 0x6058
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#define CAS_MAC_JAM_SIZE 0x605c
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#define CAS_MAC_ATTEMPT_LIMIT 0x6060
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#define CAS_MAC_CONTROL_TYPE 0x6064
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#define CAS_MAC_ADDR0 0x6080 /* Normal MAC address 0 */
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#define CAS_MAC_ADDR1 0x6084
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#define CAS_MAC_ADDR2 0x6088
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#define CAS_MAC_ADDR3 0x608c /* Alternate MAC address 0 */
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#define CAS_MAC_ADDR4 0x6090
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#define CAS_MAC_ADDR5 0x6094
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#define CAS_MAC_ADDR42 0x6128 /* Control MAC address 0 */
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#define CAS_MAC_ADDR43 0x612c
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#define CAS_MAC_ADDR44 0x6130
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#define CAS_MAC_ADDR_FILTER0 0x614c
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#define CAS_MAC_ADDR_FILTER1 0x6150
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#define CAS_MAC_ADDR_FILTER2 0x6154
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#define CAS_MAC_ADR_FLT_MASK1_2 0x6158 /* Address filter mask 1,2 */
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#define CAS_MAC_ADR_FLT_MASK0 0x615c /* Address filter mask 0 reg */
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#define CAS_MAC_HASH0 0x6160 /* Hash table 0 */
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#define CAS_MAC_HASH1 0x6164
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#define CAS_MAC_HASH2 0x6168
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#define CAS_MAC_HASH3 0x616c
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#define CAS_MAC_HASH4 0x6170
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#define CAS_MAC_HASH5 0x6174
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#define CAS_MAC_HASH6 0x6178
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#define CAS_MAC_HASH7 0x617c
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#define CAS_MAC_HASH8 0x6180
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#define CAS_MAC_HASH9 0x6184
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#define CAS_MAC_HASH10 0x6188
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#define CAS_MAC_HASH11 0x618c
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#define CAS_MAC_HASH12 0x6190
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#define CAS_MAC_HASH13 0x6194
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#define CAS_MAC_HASH14 0x6198
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#define CAS_MAC_HASH15 0x619c
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#define CAS_MAC_NORM_COLL_CNT 0x61a0 /* Normal collision counter */
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#define CAS_MAC_FIRST_COLL_CNT 0x61a4 /* 1st successful collision cntr */
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#define CAS_MAC_EXCESS_COLL_CNT 0x61a8 /* Excess collision counter */
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#define CAS_MAC_LATE_COLL_CNT 0x61ac /* Late collision counter */
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#define CAS_MAC_DEFER_TMR_CNT 0x61b0 /* defer timer counter */
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#define CAS_MAC_PEAK_ATTEMPTS 0x61b4
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#define CAS_MAC_RX_FRAME_COUNT 0x61b8
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#define CAS_MAC_RX_LEN_ERR_CNT 0x61bc
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#define CAS_MAC_RX_ALIGN_ERR 0x61c0
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#define CAS_MAC_RX_CRC_ERR_CNT 0x61c4
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#define CAS_MAC_RX_CODE_VIOL 0x61c8
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#define CAS_MAC_RANDOM_SEED 0x61cc
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#define CAS_MAC_MAC_STATE 0x61d0 /* MAC sstate machine reg */
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/* CAS_MAC_SEND_PAUSE_CMD register bits */
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#define CAS_MAC_PAUSE_CMD_TIME 0x0000ffff
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#define CAS_MAC_PAUSE_CMD_SEND 0x00010000
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/* CAS_MAC_TX_STATUS and _MASK register bits */
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#define CAS_MAC_TX_XMIT_DONE 0x00000001
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#define CAS_MAC_TX_UNDERRUN 0x00000002
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#define CAS_MAC_TX_PKT_TOO_LONG 0x00000004
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#define CAS_MAC_TX_NCC_EXP 0x00000008 /* Normal collision cnt exp */
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#define CAS_MAC_TX_ECC_EXP 0x00000010
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#define CAS_MAC_TX_LCC_EXP 0x00000020
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#define CAS_MAC_TX_FCC_EXP 0x00000040
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#define CAS_MAC_TX_DEFER_EXP 0x00000080
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#define CAS_MAC_TX_PEAK_EXP 0x00000100
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/* CAS_MAC_RX_STATUS and _MASK register bits */
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#define CAS_MAC_RX_DONE 0x00000001
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#define CAS_MAC_RX_OVERFLOW 0x00000002
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#define CAS_MAC_RX_FRAME_CNT 0x00000004
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#define CAS_MAC_RX_ALIGN_EXP 0x00000008
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#define CAS_MAC_RX_CRC_EXP 0x00000010
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#define CAS_MAC_RX_LEN_EXP 0x00000020
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#define CAS_MAC_RX_CVI_EXP 0x00000040 /* Code violation */
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/* CAS_MAC_CONTROL_STATUS and CAS_MAC_CONTROL_MASK register bits */
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#define CAS_MAC_PAUSED 0x00000001 /* Pause received */
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#define CAS_MAC_PAUSE 0x00000002 /* enter pause state */
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#define CAS_MAC_RESUME 0x00000004 /* exit pause state */
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#define CAS_MAC_PAUSE_TIME 0xffff0000
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/* CAS_MAC_XIF_CONFIG register bits */
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#define CAS_MAC_XIF_TX_MII_ENA 0x00000001 /* Enable XIF output drivers */
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#define CAS_MAC_XIF_MII_LOOPBK 0x00000002 /* Enable MII loopback mode */
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#define CAS_MAC_XIF_ECHO_DISABL 0x00000004 /* Disable echo */
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#define CAS_MAC_XIF_GMII_MODE 0x00000008 /* Select GMII/MII mode */
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#define CAS_MAC_XIF_MII_BUF_ENA 0x00000010 /* Enable MII recv buffers */
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#define CAS_MAC_XIF_LINK_LED 0x00000020 /* force link LED active */
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#define CAS_MAC_XIF_FDPLX_LED 0x00000040 /* force FDPLX LED active */
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/* CAS_MAC_SLOT_TIME register bits */
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#define CAS_MAC_SLOT_INT 0x40
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#define CAS_MAC_SLOT_EXT 0x200 /* external phy */
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/* CAS_MAC_TX_CONFIG register bits */
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#define CAS_MAC_TX_ENABLE 0x00000001 /* TX enable */
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#define CAS_MAC_TX_IGN_CARRIER 0x00000002 /* Ignore carrier sense */
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#define CAS_MAC_TX_IGN_COLLIS 0x00000004 /* ignore collisions */
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#define CAS_MAC_TX_ENA_IPG0 0x00000008 /* extend Rx-to-TX IPG */
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#define CAS_MAC_TX_NGU 0x00000010 /* Never give up */
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#define CAS_MAC_TX_NGU_LIMIT 0x00000020 /* Never give up limit */
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#define CAS_MAC_TX_NO_BACKOFF 0x00000040
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#define CAS_MAC_TX_SLOWDOWN 0x00000080
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#define CAS_MAC_TX_NO_FCS 0x00000100 /* no FCS will be generated */
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#define CAS_MAC_TX_CARR_EXTEND 0x00000200 /* Ena TX Carrier Extension */
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/* Carrier Extension is required for half duplex Gbps operation */
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/* CAS_MAC_RX_CONFIG register bits */
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#define CAS_MAC_RX_ENABLE 0x00000001 /* RX enable */
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#define CAS_MAC_RX_STRIP_PAD 0x00000002 /* strip pad bytes */
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#define CAS_MAC_RX_STRIP_CRC 0x00000004
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#define CAS_MAC_RX_PROMISCUOUS 0x00000008 /* promiscuous mode */
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#define CAS_MAC_RX_PROMISC_GRP 0x00000010 /* promiscuous group mode */
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#define CAS_MAC_RX_HASH_FILTER 0x00000020 /* enable hash filter */
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#define CAS_MAC_RX_ADDR_FILTER 0x00000040 /* enable address filter */
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#define CAS_MAC_RX_ERRCHK_DIS 0x00000080 /* disable error checking */
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#define CAS_MAC_RX_CARR_EXTEND 0x00000100 /* Ena RX Carrier Extension */
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/*
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* Carrier Extension enables reception of packet bursts generated by
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* senders with carrier extension enabled.
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*/
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/* CAS_MAC_CONTROL_CONFIG bits */
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#define CAS_MAC_CC_TX_PAUSE 0x00000001 /* send pause enabled */
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#define CAS_MAC_CC_RX_PAUSE 0x00000002 /* receive pause enabled */
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#define CAS_MAC_CC_PASS_PAUSE 0x00000004 /* pass pause up */
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/* Cassini MIF registers */
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/* Bit bang registers use low bit only */
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#define CAS_MIF_BB_CLOCK 0x6200 /* bit bang clock */
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#define CAS_MIF_BB_DATA 0x6204 /* bit bang data */
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#define CAS_MIF_BB_OUTPUT_ENAB 0x6208
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#define CAS_MIF_FRAME 0x620c /* MIF frame - ctl and data */
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#define CAS_MIF_CONFIG 0x6210
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#define CAS_MIF_INTERRUPT_MASK 0x6214
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#define CAS_MIF_BASIC_STATUS 0x6218
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#define CAS_MIF_STATE_MACHINE 0x621c
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/* CAS_MIF_FRAME bits */
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#define CAS_MIF_FRAME_DATA 0x0000ffff
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#define CAS_MIF_FRAME_TA0 0x00010000 /* TA bit, 1 for completion */
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#define CAS_MIF_FRAME_TA1 0x00020000 /* TA bits */
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#define CAS_MIF_FRAME_REG_ADDR 0x007c0000
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#define CAS_MIF_FRAME_PHY_ADDR 0x0f800000 /* phy address, should be 0 */
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#define CAS_MIF_FRAME_OP 0x30000000 /* operation - write/read */
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#define CAS_MIF_FRAME_START 0xc0000000 /* START bits */
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#define CAS_MIF_FRAME_READ 0x60020000
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#define CAS_MIF_FRAME_WRITE 0x50020000
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#define CAS_MIF_REG_SHIFT 18
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#define CAS_MIF_PHY_SHIFT 23
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/* CAS_MIF_CONFIG register bits */
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#define CAS_MIF_CONFIG_PHY_SEL 0x00000001 /* PHY select, 0=MDIO0 */
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#define CAS_MIF_CONFIG_POLL_ENA 0x00000002 /* poll enable */
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#define CAS_MIF_CONFIG_BB_ENA 0x00000004 /* bit bang enable */
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#define CAS_MIF_CONFIG_REG_ADR 0x000000f8 /* poll register address */
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#define CAS_MIF_CONFIG_MDI0 0x00000100 /* MDIO_0 Data/MDIO_0 atached */
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#define CAS_MIF_CONFIG_MDI1 0x00000200 /* MDIO_1 Data/MDIO_1 atached */
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#define CAS_MIF_CONFIG_PHY_ADR 0x00007c00 /* poll PHY address */
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/* MDI0 is onboard transceiver MID1 is external, PHYAD for both is 0 */
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/* CAS_MIF_BASIC_STATUS and CAS_MIF_INTERRUPT_MASK bits */
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#define CAS_MIF_STATUS 0x0000ffff
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#define CAS_MIF_BASIC 0xffff0000
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/*
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* The Basic part is the last value read in the POLL field of the config
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* register.
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*
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* The status part indicates the bits that have changed.
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*/
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/* Cassini PCS/Serial link registers */
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#define CAS_MII_CONTROL 0x9000
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#define CAS_MII_STATUS 0x9004
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#define CAS_MII_ANAR 0x9008 /* MII advertisement reg */
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#define CAS_MII_ANLPAR 0x900c /* Link Partner Ability Reg */
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#define CAS_MII_CONFIG 0x9010
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#define CAS_MII_STATE_MACHINE 0x9014
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#define CAS_MII_INTERRUP_STATUS 0x9018 /* PCS interrupt state */
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#define CAS_MII_DATAPATH_MODE 0x9050
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#define CAS_MII_SLINK_CONTROL 0x9054 /* Serial link control */
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#define CAS_MII_OUTPUT_SELECT 0x9058
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#define CAS_MII_SLINK_STATUS 0x905c /* serial link status */
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#define CAS_MII_PACKET_COUNT 0x9060
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/* CAS_MII_CONTROL bits */
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#define CAS_MII_CONTROL_RESET 0x00008000
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#define CAS_MII_CONTROL_LOOPBK 0x00004000 /* 10-bit i/f loopback */
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#define CAS_MII_CONTROL_1000M 0x00002000 /* speed select, always 0 */
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#define CAS_MII_CONTROL_AUTONEG 0x00001000 /* auto negotiation enabled */
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#define CAS_MII_CONTROL_POWERDN 0x00000800
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#define CAS_MII_CONTROL_ISOLATE 0x00000400 /* isolate phy from mii */
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#define CAS_MII_CONTROL_RAN 0x00000200 /* restart auto negotiation */
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#define CAS_MII_CONTROL_FDUPLEX 0x00000100 /* full duplex, always 0 */
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#define CAS_MII_CONTROL_COL_TST 0x00000080 /* collision test */
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/* CAS_MII_STATUS reg - PCS "BMSR" (Basic Mode Status Reg) */
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#define CAS_MII_STATUS_GB_FDX 0x00000400 /* can perform GBit FDX */
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#define CAS_MII_STATUS_GB_HDX 0x00000200 /* can perform GBit HDX */
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#define CAS_MII_STATUS_UNK 0x00000100
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#define CAS_MII_STATUS_ANEG_CPT 0x00000020 /* auto negotiate compete */
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#define CAS_MII_STATUS_REM_FLT 0x00000010 /* remote fault detected */
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#define CAS_MII_STATUS_ACFG 0x00000008 /* can auto negotiate */
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#define CAS_MII_STATUS_LINK_STS 0x00000004 /* link status */
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#define CAS_MII_STATUS_JABBER 0x00000002 /* jabber condition detected */
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#define CAS_MII_STATUS_EXTCAP 0x00000001 /* extended register capability */
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/* CAS_MII_ANAR and CAS_MII_ANLPAR reg bits */
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#define CAS_MII_ANEG_NP 0x00008000 /* next page bit */
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#define CAS_MII_ANEG_ACK 0x00004000 /* ack reception of */
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/* Link Partner Capability */
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#define CAS_MII_ANEG_RF 0x00003000 /* advertise remote fault cap */
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#define CAS_MII_ANEG_ASYM_PAUSE 0x00000100 /* asymmetric pause */
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#define CAS_MII_ANEG_SYM_PAUSE 0x00000080 /* symmetric pause */
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#define CAS_MII_ANEG_HLF_DUPLX 0x00000040
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#define CAS_MII_ANEG_FUL_DUPLX 0x00000020
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/* CAS_MII_CONFIG reg */
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#define CAS_MII_CONFIG_TIMER 0x0000000e /* link monitor timer values */
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#define CAS_MII_CONFIG_ANTO 0x00000020 /* 10ms ANEG timer override */
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#define CAS_MII_CONFIG_JS 0x00000018 /* Jitter Study, 0 normal
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* 1 high freq, 2 low freq */
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#define CAS_MII_CONFIG_SDL 0x00000004 /* Signal Detect active low */
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#define CAS_MII_CONFIG_SDO 0x00000002 /* Signal Detect Override */
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#define CAS_MII_CONFIG_ENABLE 0x00000001 /* Enable PCS */
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/*
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* CAS_MII_STATE_MACHINE
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* XXX These are best guesses from observed behavior.
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*/
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#define CAS_MII_FSM_STOP 0x00000000 /* stopped */
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#define CAS_MII_FSM_RUN 0x00000001 /* running */
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#define CAS_MII_FSM_UNKWN 0x00000100 /* unknown */
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#define CAS_MII_FSM_DONE 0x00000101 /* complete */
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/*
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* CAS_MII_INTERRUP_STATUS reg
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* No mask register; mask with the global interrupt mask register.
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|
*/
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#define CAS_MII_INTERRUP_LINK 0x00000002 /* PCS link status change */
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/* CAS_MII_DATAPATH_MODE reg */
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#define CAS_MII_DATAPATH_SERIAL 0x00000001 /* Serial link */
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#define CAS_MII_DATAPATH_SERDES 0x00000002 /* Use PCS via 10bit interfac */
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#define CAS_MII_DATAPATH_MII 0x00000004 /* Use {G}MII, not PCS */
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#define CAS_MII_DATAPATH_MIIOUT 0x00000008 /* enable serial output on GMII */
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|
|
/* CAS_MII_SLINK_CONTROL reg */
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|
#define CAS_MII_SLINK_LOOPBACK 0x00000001 /* enable loopback at sl, logic
|
|
* reversed for SERDES */
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#define CAS_MII_SLINK_EN_SYNC_D 0x00000002 /* enable sync detection */
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#define CAS_MII_SLINK_LOCK_REF 0x00000004 /* lock reference clock */
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#define CAS_MII_SLINK_EMPHASIS 0x00000008 /* enable emphasis */
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|
#define CAS_MII_SLINK_SELFTEST 0x000001c0
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|
#define CAS_MII_SLINK_POWER_OFF 0x00000200 /* Power down serial link */
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|
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|
/* CAS_MII_SLINK_STATUS reg */
|
|
#define CAS_MII_SLINK_TEST 0x00000000 /* undergoing test */
|
|
#define CAS_MII_SLINK_LOCKED 0x00000001 /* waiting 500us lockrefn */
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|
#define CAS_MII_SLINK_COMMA 0x00000002 /* waiting for comma detect */
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|
#define CAS_MII_SLINK_SYNC 0x00000003 /* recv data synchronized */
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|
|
/* Wired PHY addresses */
|
|
#define CAS_PHYAD_INTERNAL 1
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|
#define CAS_PHYAD_EXTERNAL 0
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|
|
/*
|
|
* Cassini ring structures.
|
|
*/
|
|
|
|
/* Descriptor rings */
|
|
struct cas_desc {
|
|
uint64_t cd_flags;
|
|
uint64_t cd_addr;
|
|
};
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|
|
|
/* Transmit flags */
|
|
#define CAS_TD_BUFSIZE 0x0000000000007fffLL
|
|
#define CAS_TD_CXSUM_START 0x00000000001f8000LL /* Cxsum start offset */
|
|
#define CAS_TD_CXSUM_STARTSHFT 15
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|
#define CAS_TD_CXSUM_STUFF 0x000000001fe00000LL /* Cxsum stuff offset */
|
|
#define CAS_TD_CXSUM_STUFFSHFT 21
|
|
#define CAS_TD_CXSUM_ENABLE 0x0000000020000000LL /* Cxsum generation enable */
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|
#define CAS_TD_END_OF_PACKET 0x0000000040000000LL
|
|
#define CAS_TD_START_OF_PACKET 0x0000000080000000LL
|
|
#define CAS_TD_INTERRUPT_ME 0x0000000100000000LL /* Interrupt me now */
|
|
#define CAS_TD_NO_CRC 0x0000000200000000LL /* do not insert crc */
|
|
/*
|
|
* Only need to set CAS_TD_CXSUM_ENABLE, CAS_TD_CXSUM_STUFF,
|
|
* CAS_TD_CXSUM_START, and CAS_TD_INTERRUPT_ME in 1st descriptor of a group.
|
|
*/
|
|
|
|
/* Completion ring */
|
|
struct cas_comp {
|
|
u_int64_t cc_word[4];
|
|
};
|
|
|
|
#define CAS_RC0_TYPE 0xc000000000000000ULL
|
|
#define CAS_RC0_RELEASE_HDR 0x2000000000000000ULL
|
|
#define CAS_RC0_RELEASE_DATA 0x1000000000000000ULL
|
|
#define CAS_RC0_SPLIT 0x0400000000000000ULL
|
|
#define CAS_RC0_SKIP_MASK 0x0180000000000000ULL
|
|
#define CAS_RC0_SKIP_SHIFT 55
|
|
#define CAS_RC0_DATA_IDX_MASK 0x007ffe0000000000ULL
|
|
#define CAS_RC0_DATA_IDX_SHIFT 41
|
|
#define CAS_RC0_DATA_OFF_MASK 0x000001fff8000000ULL
|
|
#define CAS_RC0_DATA_OFF_SHIFT 27
|
|
#define CAS_RC0_DATA_LEN_MASK 0x0000000007ffe000ULL
|
|
#define CAS_RC0_DATA_LEN_SHIFT 13
|
|
|
|
#define CAS_RC0_SKIP(w) \
|
|
(((w) & CAS_RC0_SKIP_MASK) >> CAS_RC0_SKIP_SHIFT)
|
|
#define CAS_RC0_DATA_IDX(w) \
|
|
(((w) & CAS_RC0_DATA_IDX_MASK) >> CAS_RC0_DATA_IDX_SHIFT)
|
|
#define CAS_RC0_DATA_OFF(w) \
|
|
(((w) & CAS_RC0_DATA_OFF_MASK) >> CAS_RC0_DATA_OFF_SHIFT)
|
|
#define CAS_RC0_DATA_LEN(w) \
|
|
(((w) & CAS_RC0_DATA_LEN_MASK) >> CAS_RC0_DATA_LEN_SHIFT)
|
|
|
|
#define CAS_RC1_HDR_IDX_MASK 0xfffc000000000000ULL
|
|
#define CAS_RC1_HDR_IDX_SHIFT 50
|
|
#define CAS_RC1_HDR_OFF_MASK 0x0003f00000000000ULL
|
|
#define CAS_RC1_HDR_OFF_SHIFT 44
|
|
#define CAS_RC1_HDR_LEN_MASK 0x00000ff800000000ULL
|
|
#define CAS_RC1_HDR_LEN_SHIFT 35
|
|
|
|
#define CAS_RC1_HDR_IDX(w) \
|
|
(((w) & CAS_RC1_HDR_IDX_MASK) >> CAS_RC1_HDR_IDX_SHIFT)
|
|
#define CAS_RC1_HDR_OFF(w) \
|
|
(((w) & CAS_RC1_HDR_OFF_MASK) >> CAS_RC1_HDR_OFF_SHIFT)
|
|
#define CAS_RC1_HDR_LEN(w) \
|
|
(((w) & CAS_RC1_HDR_LEN_MASK) >> CAS_RC1_HDR_LEN_SHIFT)
|
|
|
|
#define CAS_RC3_OWN 0x0000080000000000ULL /* Owned by hardware */
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|
|
|
#endif /* _IF_CASREG_H */
|