352 lines
11 KiB
C
352 lines
11 KiB
C
/* $NetBSD: cpu.h,v 1.25 1995/09/14 02:48:09 briggs Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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* Copyright (c) 1982, 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1992, 1993 BCDL Labs. All rights reserved.
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* Allen Briggs, Chris Caputo, Michael Finch, Brad Grantham, Lawrence Kesteloot
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* Redistribution of this source code or any part thereof is permitted,
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* provided that the following conditions are met:
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* 1) Utilized source contains the copyright message above, this list
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* of conditions, and the following disclaimer.
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* 2) Binary objects containing compiled source reproduce the
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* copyright notice above on startup.
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*
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* CAVEAT: This source code is provided "as-is" by BCDL Labs, and any
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* warranties of ANY kind are disclaimed. We don't even claim that it
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* won't crash your hard disk. Basically, we want a little credit if
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* it works, but we don't want to get mail-bombed if it doesn't.
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*/
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/*
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* from: Utah $Hdr: cpu.h 1.16 91/03/25$
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*
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* @(#)cpu.h 7.7 (Berkeley) 6/27/91
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*/
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/*
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ALICE
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BG -- Sat May 23 23:58:23 EDT 1992
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Exported defines and stuff unique to mac68k.
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A lot of this stuff is really specific to the m68k, not just the macs,
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but there isn't time to do anything about that right now...
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*/
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#ifndef _MACHINE_CPU_H_
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#define _MACHINE_CPU_H_ 1
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/*
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* definitions of cpu-dependent requirements
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* referenced in generic code
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*/
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#define cpu_swapin(p) /* nothing */
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#define cpu_wait(p) /* nothing */
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#define cpu_setstack(p, ap) (p)->p_md.md_regs[SP] = ap
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#define cpu_swapout(p)
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/*
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* Arguments to hardclock, softclock and gatherstats
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* encapsulate the previous machine state in an opaque
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* clockframe; for hp300, use just what the hardware
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* leaves on the stack.
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*/
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struct clockframe {
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u_short sr;
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u_long pc;
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u_short vo;
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};
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#define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0)
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#define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0)
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#define CLKF_PC(framep) ((framep)->pc)
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#define CLKF_INTR(framep) (0) /* XXX should use PSL_M (see hp300) */
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/*
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* Preempt the current process if in interrupt from user mode,
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* or after the current trap/syscall if in system mode.
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*/
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#define need_resched() { want_resched++; aston(); }
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/*
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* Give a profiling tick to the current process from the softclock
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* interrupt. Request an ast to send us through trap(),
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* marking the proc as needing a profiling tick.
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*/
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#define need_proftick(p) ( (p)->p_flag |= P_OWEUPC, aston() )
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/*
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* Notify the current process (p) that it has a signal pending,
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* process as soon as possible.
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*/
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#define signotify(p) aston()
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#define aston() (astpending++)
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int astpending; /* need to trap before returning to user mode */
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int want_resched; /* resched() was called */
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/*
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* simulated software interrupt register
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*/
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extern unsigned char ssir;
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#define SIR_NET 0x1
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#define SIR_CLOCK 0x2
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#define SIR_SERIAL 0x4
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#define siroff(x) ssir &= ~(x)
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#define setsoftnet() ssir |= SIR_NET
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#define setsoftclock() ssir |= SIR_CLOCK
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#define setsoftserial() ssir |= SIR_SERIAL
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#define CPU_CONSDEV 1
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#define CPU_MAXID 2
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#define CTL_MACHDEP_NAMES { \
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{ 0, 0 }, \
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{ "console_device", CTLTYPE_STRUCT }, \
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}
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/* values for machineid --
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* These are equivalent to the MacOS Gestalt values. */
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#define MACH_MACII 6
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#define MACH_MACIIX 7
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#define MACH_MACIICX 8
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#define MACH_MACSE30 9
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#define MACH_MACIICI 11
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#define MACH_MACIIFX 13
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#define MACH_MACIISI 18
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#define MACH_MACQ900 20
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#define MACH_MACPB170 21
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#define MACH_MACQ700 22
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#define MACH_MACCLASSICII 23
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#define MACH_MACPB100 24
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#define MACH_MACPB140 25
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#define MACH_MACQ950 26
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#define MACH_MACLCIII 27
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#define MACH_MACPB210 29
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#define MACH_MACC650 30
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#define MACH_MACPB230 32
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#define MACH_MACPB180 33
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#define MACH_MACPB160 34
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#define MACH_MACQ800 35
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#define MACH_MACQ650 36
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#define MACH_MACLCII 37
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#define MACH_MACPB250 38
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#define MACH_MACIIVI 44
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#define MACH_MACP600 45
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#define MACH_MACIIVX 48
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#define MACH_MACCCLASSIC 49
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#define MACH_MACPB165C 50
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#define MACH_MACC610 52
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#define MACH_MACQ610 53
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#define MACH_MACPB145 54
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#define MACH_MACLC520 56
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#define MACH_MACC660AV 60
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#define MACH_MACP460 62
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#define MACH_MACPB180C 71
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#define MACH_MACPB270 77
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#define MACH_MACQ840AV 78
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#define MACH_MACP550 80
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#define MACH_MACPB165 84
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#define MACH_MACTV 88
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#define MACH_MACLC475 89
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#define MACH_MACLC575 92
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#define MACH_MACQ605 94
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/*
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* Machine classes. These define subsets of the above machines.
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*/
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#define MACH_CLASSH 0x0000 /* Hopeless cases... */
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#define MACH_CLASSII 0x0001 /* MacII class */
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#define MACH_CLASSIIci 0x0004 /* Have RBV, but no Egret */
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#define MACH_CLASSIIsi 0x0005 /* Similar to IIci -- Have Egret. */
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#define MACH_CLASSIIvx 0x0006 /* Similar to IIsi -- different via2 emul? */
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#define MACH_CLASSLC 0x0007 /* Low-Cost/Performa/Wal-Mart Macs. */
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#define MACH_CLASSPB 0x0008 /* Powerbooks. Power management. */
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#define MACH_CLASSIIfx 0x0080 /* The IIfx is in a class by itself. */
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#define MACH_CLASSQ 0x0100 /* Centris/Quadras. */
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#define MACH_68020 0
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#define MACH_68030 1
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#define MACH_68040 2
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#define MACH_PENTIUM 3 /* 66 and 99 MHz versions *only* */
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/* Defines for mmutype */
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#define MMU_68040 -2
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#define MMU_68030 -1
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/* #define MMU_HP 0 Just a reminder as to where this came from. */
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#define MMU_68851 1
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#ifdef _KERNEL
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struct mac68k_machine_S {
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int cpu_model_index;
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/*
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* Misc. info from booter.
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*/
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int machineid;
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int mach_processor;
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int mach_memsize;
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int booter_version;
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/*
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* Debugging flags.
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*/
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int do_graybars;
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int serial_boot_echo;
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int serial_console;
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/*
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* Misc. hardware info.
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*/
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int scsi80; /* Has NCR 5380 */
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int scsi96; /* Has NCR 53C96 */
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int scsi96_2; /* Has 2nd 53C96 */
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int sonic; /* Has SONIC e-net */
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int sccClkConst; /* "Constant" for SCC bps */
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};
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/* What kind of model is this */
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struct cpu_model_info {
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int machineid; /* MacOS Gestalt value. */
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char *model_major; /* Make this distinction to save a few */
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char *model_minor; /* bytes--might be useful, too. */
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int class; /* Rough class of machine. */
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/* forwarded romvec_s is defined in mac68k/macrom.h */
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struct romvec_s *rom_vectors; /* Pointer to our known rom vectors */
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};
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extern struct cpu_model_info *current_mac_model;
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extern unsigned long IOBase; /* Base address of I/O */
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extern unsigned long NuBusBase; /* Base address of NuBus */
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extern struct mac68k_machine_S mac68k_machine;
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extern int mmutype ;
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extern unsigned long load_addr;
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#endif /* _KERNEL */
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/* physical memory sections */
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#define ROMBASE (0x40800000)
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#define ROMLEN (0x01000000) /* 16MB should be plenty! */
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#define ROMMAPSIZE btoc(ROMLEN) /* 16k of page tables. */
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/* This should not be used. Use IOBase, instead. */
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#define INTIOBASE (0x50000000)
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#define INTIOTOP (IOBase+0x01000000)
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#define IIOMAPSIZE btoc(0x01000000)
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/* XXX -- Need to do something about superspace.
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* Technically, NuBus superspace starts at 0x60000000, but no
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* known Macintosh has used any slot lower numbered than 9, and
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* the super space is defined as 0xS000 0000 through 0xSFFF FFFF
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* where S is the slot number--ranging from 0x9 - 0xE.
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*/
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#define NBSBASE 0x90000000
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#define NBSTOP 0xF0000000
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#define NBBASE 0xF9000000 /* NUBUS space */
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#define NBTOP 0xFF000000 /* NUBUS space */
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#define NBMAPSIZE btoc(NBTOP-NBBASE) /* ~ 96 megs */
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#define NBMEMSIZE 0x01000000 /* 16 megs per card */
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#define NBROMOFFSET 0x00FF0000 /* Last 64K == ROM */
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/*
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* 68851 and 68030 MMU
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*/
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#define PMMU_LVLMASK 0x0007
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#define PMMU_INV 0x0400
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#define PMMU_WP 0x0800
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#define PMMU_ALV 0x1000
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#define PMMU_SO 0x2000
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#define PMMU_LV 0x4000
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#define PMMU_BE 0x8000
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#define PMMU_FAULT (PMMU_WP|PMMU_INV)
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/*
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* 68040 MMU
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*/
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#define MMU4_RES 0x001
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#define MMU4_TTR 0x002
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#define MMU4_WP 0x004
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#define MMU4_MOD 0x010
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#define MMU4_CMMASK 0x060
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#define MMU4_SUP 0x080
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#define MMU4_U0 0x100
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#define MMU4_U1 0x200
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#define MMU4_GLB 0x400
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#define MMU4_BE 0x800
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/* 680X0 function codes */
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#define FC_USERD 1 /* user data space */
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#define FC_USERP 2 /* user program space */
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#define FC_SUPERD 5 /* supervisor data space */
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#define FC_SUPERP 6 /* supervisor program space */
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#define FC_CPU 7 /* CPU space */
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/* fields in the 68020 cache control register */
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#define IC_ENABLE 0x0001 /* enable instruction cache */
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#define IC_FREEZE 0x0002 /* freeze instruction cache */
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#define IC_CE 0x0004 /* clear instruction cache entry */
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#define IC_CLR 0x0008 /* clear entire instruction cache */
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/* additional fields in the 68030 cache control register */
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#define IC_BE 0x0010 /* instruction burst enable */
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#define DC_ENABLE 0x0100 /* data cache enable */
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#define DC_FREEZE 0x0200 /* data cache freeze */
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#define DC_CE 0x0400 /* clear data cache entry */
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#define DC_CLR 0x0800 /* clear entire data cache */
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#define DC_BE 0x1000 /* data burst enable */
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#define DC_WA 0x2000 /* write allocate */
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#define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
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#define CACHE_OFF (DC_CLR|IC_CLR)
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#define CACHE_CLR (CACHE_ON)
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#define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
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#define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)
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/* 68040 cache control register */
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#define IC4_ENABLE 0x00008000 /* enable instruction cache */
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#define DC4_ENABLE 0x80000000 /* enable data cache */
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#define CACHE4_ON (IC4_ENABLE|DC4_ENABLE)
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#define CACHE4_OFF 0x00000000
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#endif /* !_MACHINE_CPU_H_ */
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