823b306d1e
in the current form, they complicate implementation of fast software interrupts. I'd rather get fast softints in now and may be revisit interrupt stack later.
266 lines
7.9 KiB
C
266 lines
7.9 KiB
C
/* $NetBSD: cpu.h,v 1.53 2008/03/22 03:23:27 uwe Exp $ */
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/*-
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* Copyright (c) 2002 The NetBSD Foundation, Inc. All rights reserved.
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)cpu.h 5.4 (Berkeley) 5/9/91
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*/
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/*
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* SH3/SH4 support.
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*
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* T.Horiuchi Brains Corp. 5/22/98
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*/
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#ifndef _SH3_CPU_H_
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#define _SH3_CPU_H_
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#if defined(_KERNEL_OPT)
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#include "opt_lockdebug.h"
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#endif
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#include <sh3/psl.h>
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#include <sh3/frame.h>
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#ifdef _KERNEL
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#include <sys/cpu_data.h>
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struct cpu_info {
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struct cpu_data ci_data; /* MI per-cpu data */
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cpuid_t ci_cpuid;
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int ci_mtx_count;
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int ci_mtx_oldspl;
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int ci_want_resched;
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int ci_idepth;
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};
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extern struct cpu_info cpu_info_store;
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#define curcpu() (&cpu_info_store)
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/*
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* definitions of cpu-dependent requirements
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* referenced in generic code
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*/
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#define cpu_number() 0
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/*
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* Can't swapout u-area, (__SWAP_BROKEN)
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* since we use P1 converted address for trapframe.
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*/
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#define cpu_swapin(p) /* nothing */
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#define cpu_swapout(p) panic("cpu_swapout: can't get here");
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#define cpu_proc_fork(p1, p2) /* nothing */
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/*
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* Arguments to hardclock and gatherstats encapsulate the previous
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* machine state in an opaque clockframe.
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*/
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struct clockframe {
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int spc; /* program counter at time of interrupt */
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int ssr; /* status register at time of interrupt */
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int ssp; /* stack pointer at time of interrupt */
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};
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#define CLKF_USERMODE(cf) (!KERNELMODE((cf)->ssr))
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#define CLKF_PC(cf) ((cf)->spc)
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#define CLKF_INTR(cf) (curcpu()->ci_idepth > 0)
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/*
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* This is used during profiling to integrate system time. It can safely
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* assume that the process is resident.
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*/
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#define PROC_PC(p) \
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(((struct trapframe *)(p)->p_md.md_regs)->tf_spc)
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/*
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* Preempt the current process if in interrupt from user mode,
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* or after the current trap/syscall if in system mode.
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*/
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#define cpu_need_resched(ci, flags) \
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do { \
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ci->ci_want_resched = 1; \
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if (curlwp != ci->ci_data.cpu_idlelwp) \
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aston(curlwp); \
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} while (/*CONSTCOND*/0)
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/*
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* Give a profiling tick to the current process when the user profiling
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* buffer pages are invalid. On the MIPS, request an ast to send us
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* through trap, marking the proc as needing a profiling tick.
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*/
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#define cpu_need_proftick(l) \
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do { \
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(l)->l_pflag |= LP_OWEUPC; \
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aston(l); \
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} while (/*CONSTCOND*/0)
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/*
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* Notify the current process (p) that it has a signal pending,
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* process as soon as possible.
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*/
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#define cpu_signotify(l) aston(l)
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#define aston(l) ((l)->l_md.md_astpending = 1)
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/*
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* We need a machine-independent name for this.
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*/
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#define DELAY(x) delay(x)
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#endif /* _KERNEL */
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/*
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* Logical address space of SH3/SH4 CPU.
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*/
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#define SH3_PHYS_MASK 0x1fffffff
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#define SH3_P0SEG_BASE 0x00000000 /* TLB mapped, also U0SEG */
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#define SH3_P0SEG_END 0x7fffffff
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#define SH3_P1SEG_BASE 0x80000000 /* pa == va */
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#define SH3_P1SEG_END 0x9fffffff
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#define SH3_P2SEG_BASE 0xa0000000 /* pa == va, non-cacheable */
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#define SH3_P2SEG_END 0xbfffffff
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#define SH3_P3SEG_BASE 0xc0000000 /* TLB mapped, kernel mode */
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#define SH3_P3SEG_END 0xdfffffff
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#define SH3_P4SEG_BASE 0xe0000000 /* peripheral space */
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#define SH3_P4SEG_END 0xffffffff
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#define SH3_P1SEG_TO_PHYS(x) ((uint32_t)(x) & SH3_PHYS_MASK)
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#define SH3_P2SEG_TO_PHYS(x) ((uint32_t)(x) & SH3_PHYS_MASK)
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#define SH3_PHYS_TO_P1SEG(x) ((uint32_t)(x) | SH3_P1SEG_BASE)
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#define SH3_PHYS_TO_P2SEG(x) ((uint32_t)(x) | SH3_P2SEG_BASE)
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#define SH3_P1SEG_TO_P2SEG(x) ((uint32_t)(x) | 0x20000000)
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#define SH3_P2SEG_TO_P1SEG(x) ((uint32_t)(x) & ~0x20000000)
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#ifndef __lint__
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/*
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* Switch from P1 (cached) to P2 (uncached). This used to be written
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* using gcc's assigned goto extension, but gcc4 aggressive optimizations
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* tend to optimize that away under certain circumstances.
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*/
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#define RUN_P2 \
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do { \
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register uint32_t r0 asm("r0"); \
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uint32_t pc; \
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__asm volatile( \
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" mov.l 1f, %1 ;" \
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" mova 2f, %0 ;" \
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" or %0, %1 ;" \
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" jmp @%1 ;" \
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" nop ;" \
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" .align 2 ;" \
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"1: .long 0x20000000;" \
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"2:;" \
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: "=r"(r0), "=r"(pc)); \
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} while (0)
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/*
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* Switch from P2 (uncached) back to P1 (cached). We need to be
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* running on P2 to access cache control, memory-mapped cache and TLB
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* arrays, etc. and after touching them at least 8 instructinos are
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* necessary before jumping to P1, so provide that padding here.
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*/
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#define RUN_P1 \
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do { \
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register uint32_t r0 asm("r0"); \
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uint32_t pc; \
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__asm volatile( \
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/*1*/ " mov.l 1f, %1 ;" \
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/*2*/ " mova 2f, %0 ;" \
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/*3*/ " nop ;" \
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/*4*/ " and %0, %1 ;" \
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/*5*/ " nop ;" \
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/*6*/ " nop ;" \
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/*7*/ " nop ;" \
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/*8*/ " nop ;" \
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" jmp @%1 ;" \
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" nop ;" \
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" .align 2 ;" \
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"1: .long ~0x20000000;" \
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"2:;" \
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: "=r"(r0), "=r"(pc)); \
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} while (0)
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/*
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* If RUN_P1 is the last thing we do in a function we can omit it, b/c
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* we are going to return to a P1 caller anyway, but we still need to
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* ensure there's at least 8 instructions before jump to P1.
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*/
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#define PAD_P1_SWITCH __asm volatile ("nop;nop;nop;nop;nop;nop;nop;nop;")
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#else /* __lint__ */
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#define RUN_P2 do {} while (/* CONSTCOND */ 0)
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#define RUN_P1 do {} while (/* CONSTCOND */ 0)
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#define PAD_P1_SWITCH do {} while (/* CONSTCOND */ 0)
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#endif
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#if defined(SH4)
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/* SH4 Processor Version Register */
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#define SH4_PVR_ADDR 0xff000030 /* P4 address */
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#define SH4_PVR (*(volatile uint32_t *) SH4_PVR_ADDR)
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#define SH4_PRR_ADDR 0xff000044 /* P4 address */
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#define SH4_PRR (*(volatile uint32_t *) SH4_PRR_ADDR)
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#define SH4_PVR_MASK 0xffffff00
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#define SH4_PVR_SH7750 0x04020500 /* SH7750 */
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#define SH4_PVR_SH7750S 0x04020600 /* SH7750S */
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#define SH4_PVR_SH775xR 0x04050000 /* SH775xR */
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#define SH4_PVR_SH7751 0x04110000 /* SH7751 */
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#define SH4_PRR_MASK 0xfffffff0
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#define SH4_PRR_7750R 0x00000100 /* SH7750R */
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#define SH4_PRR_7751R 0x00000110 /* SH7751R */
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#endif
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/*
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* pull in #defines for kinds of processors
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*/
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#include <machine/cputypes.h>
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/*
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* CTL_MACHDEP definitions.
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*/
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#define CPU_CONSDEV 1 /* dev_t: console terminal device */
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#define CPU_LOADANDRESET 2 /* load kernel image and reset */
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#define CPU_MAXID 3 /* number of valid machdep ids */
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#ifdef _KERNEL
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void sh_cpu_init(int, int);
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void sh_startup(void);
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void cpu_reset(void) __attribute__((__noreturn__)); /* soft reset */
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void _cpu_spin(uint32_t); /* for delay loop. */
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void delay(int);
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struct pcb;
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void savectx(struct pcb *);
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void dumpsys(void);
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#endif /* _KERNEL */
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#endif /* !_SH3_CPU_H_ */
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