200 lines
5.1 KiB
ArmAsm
200 lines
5.1 KiB
ArmAsm
/* $NetBSD: smdk2410_start.S,v 1.4 2003/08/29 12:41:12 bsh Exp $ */
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/*
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* Copyright (c) 2002, 2003 Fujitsu Component Limited
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* Copyright (c) 2002, 2003 Genetec Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of The Fujitsu Component Limited nor the name of
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* Genetec corporation may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
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* CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
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* CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <machine/asm.h>
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#include <arm/armreg.h>
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#include <arm/arm32/pte.h>
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#include <arm/arm32/pmap.h> /* for PMAP_DOMAIN_KERNEL */
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#include <arm/s3c2xx0/s3c2410reg.h> /* for S3C2410_SDRAM_START */
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#include "opt_smdk2xx0.h" /* SMDK2XX0_CLOCK_CONFIG */
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/*
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* Kernel start routine for Samsung SMDK2410.
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* This code is excuted at the very first after the kernel is loaded
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* by boot program.
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*/
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.text
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#ifndef SDRAM_START
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#define SDRAM_START S3C2410_SDRAM_START
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#endif
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#define KERNEL_TEXT_ADDR (SDRAM_START+0x00200000)
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.global _C_LABEL(smdk2410_start)
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_C_LABEL(smdk2410_start):
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/* Disable interrupt */
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mrs r0, cpsr
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orr r0, r0, #I32_bit
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msr cpsr, r0
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#ifdef SMDK2XX0_CLOCK_CONFIG
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adr r4, clock_config_data
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mov r2, #S3C2410_CLKMAN_BASE
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ldr r1, [r2, #CLKMAN_CLKSLOW]
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orr r0, r1, #CLKSLOW_SLOW
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str r0, [r2, #CLKMAN_CLKSLOW]
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nop
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nop
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ldmia r4, {r0,r3}
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str r0, [r2, #CLKMAN_CLKDIVN]
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str r3, [r2, #CLKMAN_MPLLCON]
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nop
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nop
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str r1, [r2, #CLKMAN_CLKSLOW]
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#endif
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/* Are we running on right place ? */
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adr r0, _C_LABEL(smdk2410_start)
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ldr r2, =KERNEL_TEXT_ADDR
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cmp r0, r2
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beq smdk2410_start_ram
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/*
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* move me to RAM
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*/
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ldr r1, Lcopy_size
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adr r0, _C_LABEL(smdk2410_start)
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add r1, r1, #3
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mov r1, r1, LSR #2
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mov r4, r2
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cmp r0, r2
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bhs 5f
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/* src < dest. copy from top */
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add r0,r0,r1,LSL #2
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add r2,r2,r1,LSL #2
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3: ldr r3,[r0,#-4]!
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str r3,[r2,#-4]!
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subs r1,r1,#1
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bhi 3b
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b 7f
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/* src >= dest. copy from bottom */
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5: ldr r3,[r0],#4
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str r3,[r2],#4
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subs r1,r1,#1
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bhi 5b
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7:
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/* Jump to RAM */
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ldr r0, Lstart_off
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add pc, r4, r0
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Lcopy_size: .word _edata-_C_LABEL(smdk2410_start)
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Lstart_off: .word smdk2410_start_ram-_C_LABEL(smdk2410_start)
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smdk2410_start_ram:
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/*
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* Kernel is loaded in SDRAM (0x30200000..), and is expected to run
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* in VA 0xc0200000..
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*/
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/* Disable MMU for a while */
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mrc p15, 0, r2, c1, c0, 0
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bic r2, r2, #CPU_CONTROL_MMU_ENABLE
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mcr p15, 0, r2, c1, c0, 0
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nop
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nop
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nop
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mov r0,#SDRAM_START /* pagetable */
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adr r4, mmu_init_table
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b 2f
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1:
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str r3, [r0, r2]
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add r2, r2, #4
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add r3, r3, #(L1_S_SIZE)
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adds r1, r1, #-1
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bhi 1b
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2:
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ldmia r4!, {r1,r2,r3} /* # of sections, PA|attr, VA */
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cmp r1, #0
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bne 1b
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mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
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mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
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/* Set the Domain Access register. Very important! */
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mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
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mcr p15, 0, r0, c3, c0, 0
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/* Enable MMU */
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #CPU_CONTROL_MMU_ENABLE
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mcr p15, 0, r0, c1, c0, 0
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nop
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nop
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nop
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/* Jump to kernel code in TRUE VA */
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adr r0, Lstart
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ldr pc, [r0]
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Lstart:
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.word start
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.macro clock_data hdivn, pdivn, mdiv, pdiv, sdiv
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.word (\hdivn)<<1 | \pdivn
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.word (\mdiv)<<PLLCON_MDIV_SHIFT | (\pdiv)<<PLLCON_PDIV_SHIFT | (\sdiv)<<PLLCON_SDIV_SHIFT
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.endm
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#ifdef SMDK2XX0_CLOCK_CONFIG
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clock_config_data:
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clock_data SMDK2XX0_CLOCK_CONFIG
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#endif
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#define MMU_INIT(va,pa,n_sec,attr) \
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.word n_sec ; \
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.word 4*((va)>>L1_S_SHIFT) ; \
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.word (pa)|(attr) ;
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mmu_init_table:
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/* fill all table VA==PA */
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MMU_INIT(0x00000000, 0x00000000, 1<<(32-L1_S_SHIFT), L1_TYPE_S|L1_S_AP(AP_KRW))
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/* map SDRAM VA==PA, WT cacheable */
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MMU_INIT(SDRAM_START, SDRAM_START, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
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/* map VA 0xc0000000..0xc3ffffff to PA 0x30000000..0x33ffffff */
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MMU_INIT(0xc0000000, SDRAM_START, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
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.word 0 /* end of table */
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