635 lines
20 KiB
C
635 lines
20 KiB
C
/* $NetBSD: grf_cv3dreg.h,v 1.6 2003/05/31 03:05:45 kristerw Exp $ */
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/*
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* Copyright (c) 1995 Michael Teske
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Ezra Story and by Kari
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* Mettinen.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _GRF_CV3DREG_H
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#define _GRF_CV3DREG_H
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/*
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* This is derived from ciruss driver source
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*/
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/* Extension to grfvideo_mode to support text modes.
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* This can be passed to both text & gfx functions
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* without worry. If gv.depth == 4, then the extended
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* fields for a text mode are present.
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*/
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struct grfcv3dtext_mode {
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struct grfvideo_mode gv;
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unsigned short fx; /* font x dimension */
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unsigned short fy; /* font y dimension */
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unsigned short cols; /* screen dimensions */
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unsigned short rows;
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void *fdata; /* font data */
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unsigned short fdstart;
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unsigned short fdend;
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};
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/* maximum console size */
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#define MAXROWS 200
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#define MAXCOLS 200
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/* read VGA register */
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#define vgar(ba, reg) (*((volatile caddr_t)(((caddr_t)ba)+(reg ^ 3))))
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/* write VGA register */
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#define vgaw(ba, reg, val) \
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*((volatile caddr_t)(((caddr_t)ba)+(reg ^ 3))) = ((val) & 0xff)
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/* MMIO access */
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#define ByteAccessIO(x) ( ((x) & 0x3ffc) | (((x) & 3)^3) | (((x) & 3) <<14) )
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#define vgario(ba, reg) \
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(*((volatile caddr_t)(((caddr_t)ba) + ( ByteAccessIO(reg) ))))
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#define vgawio(ba, reg, val) \
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do { \
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if (!cv3d_zorroIII) { \
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*((volatile caddr_t)(((caddr_t)cv3d_vcode_switch_base) + \
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0x04)) = (0x01 & 0xffff); \
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__asm __volatile ("nop"); \
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} \
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*((volatile caddr_t)(((caddr_t)cv3d_special_register_base) + \
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( ByteAccessIO(reg) & 0xffff ))) = ((val) & 0xff); \
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if (!cv3d_zorroIII) { \
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*((volatile caddr_t)(((caddr_t)cv3d_vcode_switch_base) + \
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0x04)) = (0x02 & 0xffff); \
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__asm __volatile ("nop"); \
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} \
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} while (0)
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/* read 32 Bit VGA register */
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#define vgar32(ba, reg) ( *((unsigned long *) (((volatile caddr_t)ba)+reg)) )
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/* write 32 Bit VGA register */
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#define vgaw32(ba, reg, val) \
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*((unsigned long *) (((volatile caddr_t)ba)+reg)) = val
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/* read 16 Bit VGA register */
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#define vgar16(ba, reg) ( *((unsigned short *) (((volatile caddr_t)ba)+reg)) )
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/* write 16 Bit VGA register */
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#define vgaw16(ba, reg, val) \
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*((unsigned short *) (((volatile caddr_t)ba)+reg)) = val
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/* XXX This is totaly untested */
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#define Select_Zorro2_FrameBuffer(flag) \
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do { \
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*((volatile caddr_t)(((caddr_t)cv3d_vcode_switch_base) + \
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0x08)) = ((flag * 0x40) & 0xffff); \
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__asm __volatile ("nop"); \
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} while (0)
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int grfcv3d_cnprobe(void);
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void grfcv3d_iteinit(struct grf_softc *);
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static __inline void GfxBusyWait(volatile caddr_t);
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static __inline void GfxFifoWait(volatile caddr_t);
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static __inline unsigned char RAttr(volatile caddr_t, short);
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static __inline unsigned char RSeq(volatile caddr_t, short);
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static __inline unsigned char RCrt(volatile caddr_t, short);
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static __inline unsigned char RGfx(volatile caddr_t, short);
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/*
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* defines for the used register addresses (mw)
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*
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* NOTE: there are some registers that have different addresses when
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* in mono or color mode. We only support color mode, and thus
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* some addresses won't work in mono-mode!
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*
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* General and VGA-registers taken from retina driver. Fixed a few
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* bugs in it. (SR and GR read address is Port + 1, NOT Port)
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*
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*/
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/* General Registers: */
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#define GREG_MISC_OUTPUT_R 0x03CC
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#define GREG_MISC_OUTPUT_W 0x03C2
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#define GREG_FEATURE_CONTROL_R 0x03CA
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#define GREG_FEATURE_CONTROL_W 0x03DA
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#define GREG_INPUT_STATUS0_R 0x03C2
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#define GREG_INPUT_STATUS1_R 0x03DA
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/* Setup Registers: */
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#define SREG_OPTION_SELECT 0x0102
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#define SREG_VIDEO_SUBS_ENABLE 0x03C3 /* Trio64: 0x46E8 */
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/* Attribute Controller: */
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#define ACT_ADDRESS 0x03C0
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#define ACT_ADDRESS_R 0x03C1
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#define ACT_ADDRESS_W 0x03C0
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#define ACT_ADDRESS_RESET 0x03DA
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#define ACT_ID_PALETTE0 0x00
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#define ACT_ID_PALETTE1 0x01
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#define ACT_ID_PALETTE2 0x02
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#define ACT_ID_PALETTE3 0x03
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#define ACT_ID_PALETTE4 0x04
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#define ACT_ID_PALETTE5 0x05
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#define ACT_ID_PALETTE6 0x06
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#define ACT_ID_PALETTE7 0x07
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#define ACT_ID_PALETTE8 0x08
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#define ACT_ID_PALETTE9 0x09
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#define ACT_ID_PALETTE10 0x0A
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#define ACT_ID_PALETTE11 0x0B
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#define ACT_ID_PALETTE12 0x0C
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#define ACT_ID_PALETTE13 0x0D
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#define ACT_ID_PALETTE14 0x0E
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#define ACT_ID_PALETTE15 0x0F
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#define ACT_ID_ATTR_MODE_CNTL 0x10
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#define ACT_ID_OVERSCAN_COLOR 0x11
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#define ACT_ID_COLOR_PLANE_ENA 0x12
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#define ACT_ID_HOR_PEL_PANNING 0x13
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#define ACT_ID_COLOR_SELECT 0x14 /* ACT_ID_PIXEL_PADDING */
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/* Graphics Controller: */
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#define GCT_ADDRESS 0x03CE
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#define GCT_ADDRESS_R 0x03CF
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#define GCT_ADDRESS_W 0x03CF
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#define GCT_ID_SET_RESET 0x00
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#define GCT_ID_ENABLE_SET_RESET 0x01
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#define GCT_ID_COLOR_COMPARE 0x02
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#define GCT_ID_DATA_ROTATE 0x03
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#define GCT_ID_READ_MAP_SELECT 0x04
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#define GCT_ID_GRAPHICS_MODE 0x05
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#define GCT_ID_MISC 0x06
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#define GCT_ID_COLOR_XCARE 0x07
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#define GCT_ID_BITMASK 0x08
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/* Sequencer: */
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#define SEQ_ADDRESS 0x03C4
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#define SEQ_ADDRESS_R 0x03C5
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#define SEQ_ADDRESS_W 0x03C5
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#define SEQ_ID_RESET 0x00
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#define SEQ_ID_CLOCKING_MODE 0x01
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#define SEQ_ID_MAP_MASK 0x02
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#define SEQ_ID_CHAR_MAP_SELECT 0x03
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#define SEQ_ID_MEMORY_MODE 0x04
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#define SEQ_ID_UNKNOWN1 0x05
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#define SEQ_ID_UNKNOWN2 0x06
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#define SEQ_ID_UNKNOWN3 0x07
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/* S3 extensions */
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#define SEQ_ID_UNLOCK_EXT 0x08
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#define SEQ_ID_MMIO_SELECT 0x09 /* Trio64: SEQ_ID_EXT_SEQ_REG9 */
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#define SEQ_ID_BUS_REQ_CNTL 0x0A
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#define SEQ_ID_EXT_MISC_SEQ 0x0B
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#define SEQ_ID_UNKNOWN4 0x0C
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#define SEQ_ID_EXT_SEQ 0x0D
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#define SEQ_ID_UNKNOWN5 0x0E
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#define SEQ_ID_UNKNOWN6 0x0F
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#define SEQ_ID_MCLK_LO 0x10
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#define SEQ_ID_MCLK_HI 0x11
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#define SEQ_ID_DCLK_LO 0x12
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#define SEQ_ID_DCLK_HI 0x13
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#define SEQ_ID_CLKSYN_CNTL_1 0x14
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#define SEQ_ID_CLKSYN_CNTL_2 0x15
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#define SEQ_ID_CLKSYN_TEST_HI 0x16 /* reserved for S3 testing of the */
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#define SEQ_ID_CLKSYN_TEST_LO 0x17 /* internal clock synthesizer */
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#define SEQ_ID_RAMDAC_CNTL 0x18
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#define SEQ_ID_MORE_MAGIC 0x1A /* not available on the Virge */
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#define SEQ_ID_SIGNAL_SELECT 0x1C
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/* CRT Controller: */
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#define CRT_ADDRESS 0x03D4
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#define CRT_ADDRESS_R 0x03D5
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#define CRT_ADDRESS_W 0x03D5
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#define CRT_ID_HOR_TOTAL 0x00
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#define CRT_ID_HOR_DISP_ENA_END 0x01
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#define CRT_ID_START_HOR_BLANK 0x02
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#define CRT_ID_END_HOR_BLANK 0x03
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#define CRT_ID_START_HOR_RETR 0x04
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#define CRT_ID_END_HOR_RETR 0x05
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#define CRT_ID_VER_TOTAL 0x06
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#define CRT_ID_OVERFLOW 0x07
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#define CRT_ID_PRESET_ROW_SCAN 0x08
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#define CRT_ID_MAX_SCAN_LINE 0x09
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#define CRT_ID_CURSOR_START 0x0A
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#define CRT_ID_CURSOR_END 0x0B
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#define CRT_ID_START_ADDR_HIGH 0x0C
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#define CRT_ID_START_ADDR_LOW 0x0D
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#define CRT_ID_CURSOR_LOC_HIGH 0x0E
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#define CRT_ID_CURSOR_LOC_LOW 0x0F
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#define CRT_ID_START_VER_RETR 0x10
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#define CRT_ID_END_VER_RETR 0x11
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#define CRT_ID_VER_DISP_ENA_END 0x12
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#define CRT_ID_SCREEN_OFFSET 0x13
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#define CRT_ID_UNDERLINE_LOC 0x14
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#define CRT_ID_START_VER_BLANK 0x15
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#define CRT_ID_END_VER_BLANK 0x16
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#define CRT_ID_MODE_CONTROL 0x17
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#define CRT_ID_LINE_COMPARE 0x18
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#define CRT_ID_GD_LATCH_RBACK 0x22
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#define CRT_ID_ACT_TOGGLE_RBACK 0x24
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#define CRT_ID_ACT_INDEX_RBACK 0x26
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/* S3 extensions: S3 VGA Registers */
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#define CRT_ID_DEVICE_HIGH 0x2D
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#define CRT_ID_DEVICE_LOW 0x2E
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#define CRT_ID_REVISION 0x2F
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#define CRT_ID_CHIP_ID_REV 0x30
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#define CRT_ID_MEMORY_CONF 0x31
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#define CRT_ID_BACKWAD_COMP_1 0x32
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#define CRT_ID_BACKWAD_COMP_2 0x33
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#define CRT_ID_BACKWAD_COMP_3 0x34
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#define CRT_ID_REGISTER_LOCK 0x35
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#define CRT_ID_CONFIG_1 0x36
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#define CRT_ID_CONFIG_2 0x37
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#define CRT_ID_REGISTER_LOCK_1 0x38
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#define CRT_ID_REGISTER_LOCK_2 0x39
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#define CRT_ID_MISC_1 0x3A
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#define CRT_ID_DISPLAY_FIFO 0x3B
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#define CRT_ID_LACE_RETR_START 0x3C
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/* S3 extensions: System Control Registers */
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#define CRT_ID_SYSTEM_CONFIG 0x40
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#define CRT_ID_BIOS_FLAG 0x41
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#define CRT_ID_LACE_CONTROL 0x42
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#define CRT_ID_EXT_MODE 0x43
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#define CRT_ID_HWGC_MODE 0x45 /* HWGC = Hardware Graphics Cursor */
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#define CRT_ID_HWGC_ORIGIN_X_HI 0x46
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#define CRT_ID_HWGC_ORIGIN_X_LO 0x47
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#define CRT_ID_HWGC_ORIGIN_Y_HI 0x48
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#define CRT_ID_HWGC_ORIGIN_Y_LO 0x49
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#define CRT_ID_HWGC_FG_STACK 0x4A
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#define CRT_ID_HWGC_BG_STACK 0x4B
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#define CRT_ID_HWGC_START_AD_HI 0x4C
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#define CRT_ID_HWGC_START_AD_LO 0x4D
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#define CRT_ID_HWGC_DSTART_X 0x4E
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#define CRT_ID_HWGC_DSTART_Y 0x4F
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/* S3 extensions: System Extension Registers */
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#define CRT_ID_EXT_SYS_CNTL_1 0x50
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#define CRT_ID_EXT_SYS_CNTL_2 0x51
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#define CRT_ID_EXT_BIOS_FLAG_1 0x52
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#define CRT_ID_EXT_MEM_CNTL_1 0x53
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#define CRT_ID_EXT_MEM_CNTL_2 0x54
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#define CRT_ID_EXT_DAC_CNTL 0x55
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#define CRT_ID_EX_SYNC_1 0x56
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#define CRT_ID_EX_SYNC_2 0x57
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#define CRT_ID_LAW_CNTL 0x58 /* LAW = Linear Address Window */
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#define CRT_ID_LAW_POS_HI 0x59
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#define CRT_ID_LAW_POS_LO 0x5A
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#define CRT_ID_GOUT_PORT 0x5C
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#define CRT_ID_EXT_HOR_OVF 0x5D
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#define CRT_ID_EXT_VER_OVF 0x5E
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#define CRT_ID_EXT_MEM_CNTL_3 0x60
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#define CRT_ID_EXT_MEM_CNTL_4 0x61 /* only available on the Virge */
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#define CRT_ID_EX_SYNC_3 0x63 /* not available on the Virge */
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#define CRT_ID_EXT_MISC_CNTL 0x65
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#define CRT_ID_EXT_MISC_CNTL_1 0x66
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#define CRT_ID_EXT_MISC_CNTL_2 0x67
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#define CRT_ID_CONFIG_3 0x68
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#define CRT_ID_EXT_SYS_CNTL_3 0x69
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#define CRT_ID_EXT_SYS_CNTL_4 0x6A
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#define CRT_ID_EXT_BIOS_FLAG_3 0x6B
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#define CRT_ID_EXT_BIOS_FLAG_4 0x6C
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#define CRT_ID_EXT_BIOS_FLAG_5 0x6D /* only available on the Virge */
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#define CRT_ID_RAMDAC_SIG_TEST 0x6E /* only available on the Virge */
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#define CRT_ID_CONFIG_4 0x6F /* only available on the Virge */
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/* Streams Processor */
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#define SP_PRIMARY_CONTROL 0x8180
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#define SP_COLOR_CHROMA_KEY_CONTROL 0x8184
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#define SP_SECONDARY_CONTROL 0x8190
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#define SP_CHROMA_KEY_UPPER_BOUND 0x8194
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#define SP_SECONDARY_CONSTANTS 0x8198
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#define SP_BLEND_CONTROL 0x81A0
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#define SP_PRIMARY_ADDRESS_0 0x81C0
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#define SP_PRIMARY_ADDRESS_1 0x81C4
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#define SP_PRIMARY_STRIDE 0x81C8
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#define SP_DOUBLE_BUFFER_LPB_SUPPORT 0x81CC
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#define SP_SECONDARY_ADDRESS_0 0x81D0
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#define SP_SECONDARY_ADDRESS_1 0x81D4
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#define SP_SECONDARY_STRIDE 0x81D8
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#define SP_OPAQUE_OVERLAY_CONTROL 0x81DC
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#define SP_K1_VERTICAL_SCALE_FACTOR 0x81E0
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#define SP_K2_VERTICAL_SCALE_FACTOR 0x81E4
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#define SP_DDA_VERTICAL_ACCUMULATOR 0x81E8
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#define SP_FIFO_CONTROL 0x81EC
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#define SP_PRIMARY_WINDOW_TOP_LEFT 0x81F0
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#define SP_PRIMARY_WINDOW_SIZE 0x81F4
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#define SP_SECONDARY_WINDOW_TOP_LEFT 0x81F8
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#define SP_SECONDARY_WINDOW_SIZE 0x81FC
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/* Memory Port Controller */
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#define MPC_FIFO_CONTROL 0x8200
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#define MPC_MIU_CONTROL 0x8204
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#define MPC_STREAMS_TIMEOUT 0x8208
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#define MPC_MISC_TIMEOUT 0x820C
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#define MPC_DMA_READ_BASE_ADDRESS 0x8220
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#define MPC_DMA_READ_STRIDE_WIDTH 0x8224
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/* Miscellaneous Registers */
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#define MR_SUBSYSTEM_STATUS_CNTL 0x8504
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#define MR_ADVANCED_FUNCTION_CONTROL 0x850C
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/* S3d Engine */
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#define S3D_BIT_BLT_RECT_FILL 0xA400
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#define S3D_LINE_2D 0xA800
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#define S3D_POLYGON_2D 0xAC00
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#define S3D_LINE_3D 0xB000
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#define S3D_TRIANGLE_3D 0xB400
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#define BLT_ADDRESS 0xA4D4
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#define BLT_SOURCE_ADDRESS 0xA4D4
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#define BLT_DEST_ADDRESS 0xA4D8
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#define BLT_CLIP_LEFT_RIGHT 0xA4DC
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#define BLT_CLIP_LEFT BLT_CLIP_LEFT_RIGHT
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#define BLT_CLIP_RIGHT 0xA4DE
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#define BLT_CLIP_TOP_BOTTOM 0xA4E0
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#define BLT_CLIP_BOTTOM BLT_CLIP_TOP_BOTTOM
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#define BLT_CLIP_TOP 0xA4E2
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#define BLT_DEST_SOURCE_PITCH 0xA4E4
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#define BLT_SOURCE_PITCH BLT_DEST_SOURCE_PITCH
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#define BLT_DEST_PITCH 0xA4E6
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#define BLT_MONO_PATTERN 0xA4E8
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#define BLT_MONO_PATTERN_0 BLT_MONO_PATTERN
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#define BLT_MONO_PATTERN_1 0xA4EC
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#define BLT_PATTERN_BG_COLOR 0xA4F0
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#define BLT_PATTERN_BG_COLOR_TRUE_COLOR BLT_PATTERN_BG_COLOR
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#define BLT_PATTERN_BG_COLOR_ALPHA BLT_PATTERN_BG_COLOR
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#define BLT_PATTERN_BG_COLOR_RED 0xA4F1
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#define BLT_PATTERN_BG_COLOR_HI_COLOR 0xA4F2
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#define BLT_PATTERN_BG_COLOR_GREEN BLT_PATTERN_BG_COLOR_HI_COLOR
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#define BLT_PATTERN_BG_COLOR_INDEX 0xA4F3
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#define BLT_PATTERN_BG_COLOR_BLUE BLT_PATTERN_BG_COLOR_INDEX
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#define BLT_PATTERN_FG_COLOR 0xA4F4
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#define BLT_PATTERN_FG_COLOR_TRUE_COLOR BLT_PATTERN_FG_COLOR
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#define BLT_PATTERN_FG_COLOR_ALPHA BLT_PATTERN_FG_COLOR
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#define BLT_PATTERN_FG_COLOR_RED 0xA4F5
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#define BLT_PATTERN_FG_COLOR_HI_COLOR 0xA4F6
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#define BLT_PATTERN_FG_COLOR_GREEN BLT_PATTERN_FG_COLOR_HI_COLOR
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#define BLT_PATTERN_FG_COLOR_INDEX 0xA4F7
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#define BLT_PATTERN_FG_COLOR_BLUE BLT_PATTERN_FG_COLOR_INDEX
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#define BLT_SOURCE_BG_COLOR 0xA4F8
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#define BLT_SOURCE_BG_COLOR_TRUE_COLOR BLT_SOURCE_BG_COLOR
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#define BLT_SOURCE_BG_COLOR_ALPHA BLT_SOURCE_BG_COLOR
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#define BLT_SOURCE_BG_COLOR_RED 0xA4F9
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#define BLT_SOURCE_BG_COLOR_HI_COLOR 0xA4FA
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#define BLT_SOURCE_BG_COLOR_GREEN BLT_SOURCE_BG_COLOR_HI_COLOR
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#define BLT_SOURCE_BG_COLOR_INDEX 0xA4FB
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#define BLT_SOURCE_BG_COLOR_BLUE BLT_SOURCE_BG_COLOR_INDEX
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#define BLT_SOURCE_FG_COLOR 0xA4FC
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#define BLT_SOURCE_FG_COLOR_TRUE_COLOR BLT_SOURCE_FG_COLOR
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#define BLT_SOURCE_FG_COLOR_ALPHA BLT_SOURCE_FG_COLOR
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#define BLT_SOURCE_FG_COLOR_RED 0xA4FD
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#define BLT_SOURCE_FG_COLOR_HI_COLOR 0xA4FE
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#define BLT_SOURCE_FG_COLOR_GREEN BLT_SOURCE_FG_COLOR_HI_COLOR
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#define BLT_SOURCE_FG_COLOR_INDEX 0xA4FF
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#define BLT_SOURCE_FG_COLOR_BLUE BLT_SOURCE_FG_COLOR_INDEX
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#define BLT_COMMAND_SET 0xA500
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#define BLT_WIDTH_HEIGHT 0xA504
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#define BLT_HEIGHT BLT_WIDTH_HEIGHT
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#define BLT_WIDTH 0xA506
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#define BLT_SOURCE_XY 0xA508
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#define BLT_SOURCE_Y BLT_SOURCE_XY
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#define BLT_SOURCE_X 0xA50A
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#define BLT_DESTINATION_XY 0xA50C
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#define BLT_DESTINATION_Y BLT_DESTINATION_XY
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#define BLT_DESTINATION_X 0xA50E
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#define L2D_ADDRESS 0xA8D4
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#define L2D_SOURCE_ADDRESS 0xA8D4
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#define L2D_DEST_ADDRESS 0xA8D8
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#define L2D_CLIP_LEFT_RIGHT 0xA8DC
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#define L2D_CLIP_LEFT L2D_CLIP_LEFT_RIGHT
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#define L2D_CLIP_RIGHT 0xA8DE
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#define L2D_CLIP_TOP_BOTTOM 0xA8E0
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#define L2D_CLIP_BOTTOM L2D_CLIP_TOP_BOTTOM
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#define L2D_CLIP_TOP 0xA8E2
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#define L2D_DEST_SOURCE_PITCH 0xA8E4
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#define L2D_SOURCE_PITCH L2D_DEST_SOURCE_PITCH
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#define L2D_DEST_PITCH 0xA8E6
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#define L2D_PAD_0 0xA8E8
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#define L2D_PATTERN_FG_COLOR_TRUE_COLOR 0xA8F4
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#define L2D_PATTERN_FG_COLOR_ALPHA L2D_PATTERN_FG_COLOR_TRUECOLOR
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#define L2D_PATTERN_FG_COLOR_RED 0xA8F5
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#define L2D_PATTERN_FG_COLOR_HI_COLOR 0xA8F6
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#define L2D_PATTERN_FG_COLOR_GREEN L2D_PATTERN_FG_COLOR_HICOLOR
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#define L2D_PATTERN_FG_COLOR_INDEX 0xA8F7
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#define L2D_PATTERN_FG_COLOR_BLUE L2D_PATTERN_FG_COLOR_INDEX
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#define L2D_PAD_1 0xA8F8
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#define L2D_COMMAND_SET 0xA900
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#define L2D_PAD_2 0xA904
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#define L2D_END_0_END_1 0xA96C
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#define L2D_END_1 L2D_END_0_END_1
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#define L2D_END_0 0xA96E
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#define L2D_DX 0xA970
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#define L2D_X_START 0xA974
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#define L2D_Y_START 0xA978
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#define L2D_Y_COUNT 0xA97C
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#define P2D_ADDRESS 0xACD4
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#define P2D_SOURCE_ADDRESS 0xACD4
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#define P2D_DEST_ADDRESS 0xACD8
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#define P2D_CLIP_LEFT_RIGHT 0xACDC
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#define P2D_CLIP_LEFT P2D_CLIP_LEFT_RIGHT
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#define P2D_CLIP_RIGHT 0xACDE
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#define P2D_CLIP_TOP_BOTTOM 0xACE0
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#define P2D_CLIP_BOTTOM P2D_CLIP_TOP_BOTTOM
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#define P2D_CLIP_TOP 0xACE2
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#define P2D_DEST_SOURCE_PITCH 0xACE4
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#define P2D_SOURCE_PITCH P2D_DEST_SOURCE_PITCH
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#define P2D_DEST_PITCH 0xACE6
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#define P2D_MONO_PATTERN 0xACE8
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#define P2D_PATTERN_BG_COLOR_TRUE_COLOR 0xACF0
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#define P2D_PATTERN_BG_COLOR_ALPHA P2D_PATTERN_BG_COLOR_TRUE_COLOR
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#define P2D_PATTERN_BG_COLOR_RED 0xACF1
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#define P2D_PATTERN_BG_COLOR_HI_COLOR 0xACF2
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#define P2D_PATTERN_BG_COLOR_GREEN P2D_PATTERN_BG_COLOR_HI_COLOR
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#define P2D_PATTERN_BG_COLOR_INDEX 0xACF3
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#define P2D_PATTERN_BG_COLOR_BLUE P2D_PATTERN_BG_COLOR_INDEX
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#define P2D_PATTERN_FG_COLOR_TRUE_COLOR 0xACF4
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#define P2D_PATTERN_FG_COLOR_ALPHA P2D_PATTERN_FG_COLOR_TRUE_COLOR
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#define P2D_PATTERN_FG_COLOR_RED 0xACF5
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#define P2D_PATTERN_FG_COLOR_HI_COLOR 0xACF6
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#define P2D_PATTERN_FG_COLOR_GREEN P2D_PATTERN_FG_COLOR_HI_COLOR
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#define P2D_PATTERN_FG_COLOR_INDEX 0xACF7
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#define P2D_PATTERN_FG_COLOR_BLUE P2D_PATTERN_FG_COLOR_INDEX
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#define P2D_PAD_1 0xACF8
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#define P2D_COMMAND_SET 0xAD00
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#define P2D_PAD_2 0xAD04
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#define P2D_RIGHT_DX 0xAD68
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#define P2D_RIGHT_X_START 0xAD6C
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#define P2D_LEFT_DX 0xAD70
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#define P2D_LEFT_X_START 0xAD74
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#define P2D_Y_START 0xAD78
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#define P2D_Y_COUNT 0xAD7C
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#define CMD_NOP (7 << 27) /* %1111 << 27 */
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#define CMD_LINE (3 << 27) /* %0011 << 27 */
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#define CMD_RECT (4 << 27) /* %0010 << 27 */
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#define CMD_POLYGON (5 << 27) /* %0101 << 27 */
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#define CMD_BITBLT (0 << 27) /* %0000 << 27 */
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#define CMD_SKIP_TRANSFER_BYTES_1 (1 << 12) /* %01 << 12 */
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#define CMD_SKIP_TRANSFER_BYTES_2 (2 << 12) /* %10 << 12 */
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#define CMD_SKIP_TRANSFER_BYTES_3 (3 << 12) /* %11 << 12 */
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#define CMD_TRANSFER_ALIGNMENT_BYTE (0 << 10) /* %00 << 10 */
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#define CMD_TRANSFER_ALIGNMENT_WORD (1 << 10) /* %01 << 10 */
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#define CMD_TRANSFER_ALIGNMENT_DOUBLEWORD (2 << 10) /* %10 << 10 */
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#define CMD_CHUNKY (0 << 2) /* %00 << 2 */
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#define CMD_HI_COLOR (1 << 2) /* %01 << 2 */
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#define CMD_TRUE_COLOR (2 << 2) /* %10 << 2 */
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#define ROP_FALSE 0x00
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#define ROP_NOR 0x10
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#define ROP_ONLYDST 0x20
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#define ROP_NOTSRC 0x30
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#define ROP_ONLYSRC 0x40
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#define ROP_NOTDST 0x50
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#define ROP_EOR 0x60
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#define ROP_NAND 0x70
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#define ROP_AND 0x80
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#define ROP_NEOR 0x90
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#define ROP_DST 0xA0
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#define ROP_NOTONLYSRC 0xB0
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#define ROP_SRC 0xC0
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#define ROP_NOTONLYDST 0xD0
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#define ROP_OR 0xE0
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#define ROP_TRUE 0xF0
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/* Pass-through */
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#if 0 /* XXX */
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#define PASS_ADDRESS 0x
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#define PASS_ADDRESS_W 0x
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#endif
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/* Video DAC */
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#define VDAC_ADDRESS 0x03C8
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#define VDAC_ADDRESS_W 0x03C8
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#define VDAC_ADDRESS_R 0x03C7
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#define VDAC_STATE 0x03C7
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#define VDAC_DATA 0x03C9
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#define VDAC_MASK 0x03C6
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#define WGfx(ba, idx, val) \
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do { vgaw(ba, GCT_ADDRESS, idx); vgaw(ba, GCT_ADDRESS_W , val); } while (0)
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#define WSeq(ba, idx, val) \
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do { vgaw(ba, SEQ_ADDRESS, idx); vgaw(ba, SEQ_ADDRESS_W , val); } while (0)
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#define WCrt(ba, idx, val) \
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do { vgaw(ba, CRT_ADDRESS, idx); vgaw(ba, CRT_ADDRESS_W , val); } while (0)
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|
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#define WAttr(ba, idx, val) \
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do { \
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unsigned char tmp;\
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tmp = vgar(ba, ACT_ADDRESS_RESET);\
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vgaw(ba, ACT_ADDRESS_W, idx);\
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vgaw(ba, ACT_ADDRESS_W, val);\
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} while (0)
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#define SetTextPlane(ba, m) \
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do { \
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WGfx(ba, GCT_ID_READ_MAP_SELECT, m & 3 );\
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WSeq(ba, SEQ_ID_MAP_MASK, (1 << (m & 3)));\
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} while (0)
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|
|
|
|
/* Gfx engine busy wait */
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|
|
|
static __inline void
|
|
GfxBusyWait (ba)
|
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volatile caddr_t ba;
|
|
{
|
|
int test;
|
|
|
|
do {
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test = vgar32(ba, MR_SUBSYSTEM_STATUS_CNTL);
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|
__asm __volatile ("nop");
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|
} while (!(test & (1 << 13)));
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|
}
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|
|
|
|
|
static __inline void
|
|
GfxFifoWait(ba)
|
|
volatile caddr_t ba;
|
|
{
|
|
#if 0 /* XXX */
|
|
int test;
|
|
|
|
do {
|
|
test = vgar32(ba, MR_SUBSYSTEM_STATUS_CNTL);
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|
} while (test & 0x0f);
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#endif
|
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}
|
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|
|
|
|
/* Special wakeup/passthrough registers on graphics boards
|
|
*
|
|
* The methods have diverged a bit for each board, so
|
|
* WPass(P) has been converted into a set of specific
|
|
* __inline functions.
|
|
*/
|
|
|
|
static __inline unsigned char
|
|
RAttr(ba, idx)
|
|
volatile caddr_t ba;
|
|
short idx;
|
|
{
|
|
|
|
vgaw(ba, ACT_ADDRESS_W, idx);
|
|
delay(0);
|
|
return vgar(ba, ACT_ADDRESS_R);
|
|
}
|
|
|
|
static __inline unsigned char
|
|
RSeq(ba, idx)
|
|
volatile caddr_t ba;
|
|
short idx;
|
|
{
|
|
vgaw(ba, SEQ_ADDRESS, idx);
|
|
return vgar(ba, SEQ_ADDRESS_R);
|
|
}
|
|
|
|
static __inline unsigned char
|
|
RCrt(ba, idx)
|
|
volatile caddr_t ba;
|
|
short idx;
|
|
{
|
|
vgaw(ba, CRT_ADDRESS, idx);
|
|
return vgar(ba, CRT_ADDRESS_R);
|
|
}
|
|
|
|
static __inline unsigned char
|
|
RGfx(ba, idx)
|
|
volatile caddr_t ba;
|
|
short idx;
|
|
{
|
|
vgaw(ba, GCT_ADDRESS, idx);
|
|
return vgar(ba, GCT_ADDRESS_R);
|
|
}
|
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|
|
#endif /* _GRF_CV3DREG_H */
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