195 lines
7.6 KiB
C
195 lines
7.6 KiB
C
/* $NetBSD: iopaaureg.h,v 1.3 2002/08/03 21:58:56 thorpej Exp $ */
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/*
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* Copyright (c) 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _XSCALE_IOPAAUREG_H_
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#define _XSCALE_IOPAAUREG_H_
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/*
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* The AAU can transfer a maximum of 16MB.
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*
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* XXX The DMA maps are > 32K if we allow the maximum number
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* XXX of DMA segments (16MB / 4K + 1) -- fix this bus_dma
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* XXX problem.
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*/
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#define AAU_MAX_XFER (16U * 1024 * 1024)
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#if 0
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#define AAU_MAX_SEGS ((AAU_MAX_XFER / PAGE_SIZE) + 1)
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#else
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#define AAU_MAX_SEGS 1024
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#endif
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/*
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* AAU I/O descriptor for operations with various numbers of inputs.
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* Note that all descriptors must be 8-word (32-byte) aligned.
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*/
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struct aau_desc_4 {
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struct aau_desc_4 *d_next; /* pointer to next (va) */
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uint32_t d_pa; /* our physical address */
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/* Hardware portion -- must be 32-byte aligned. */
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uint32_t d_nda; /* next descriptor address */
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uint32_t d_sar[4]; /* source address */
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uint32_t d_dar; /* destination address */
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uint32_t d_bc; /* byte count */
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uint32_t d_dc; /* descriptor control */
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} __attribute__((__packed__));
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struct aau_desc_8 {
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struct aau_desc_8 *d_next; /* pointer to next (va) */
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uint32_t d_pa; /* our physical address */
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/* Hardware portion -- must be 32-byte aligned. */
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uint32_t d_nda; /* next descriptor address */
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uint32_t d_sar[4]; /* source address */
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uint32_t d_dar; /* destination address */
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uint32_t d_bc; /* byte count */
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uint32_t d_dc; /* descriptor control */
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/* Mini Descriptor */
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uint32_t d_sar5_8[4]; /* source address */
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} __attribute__((__packed__));
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struct aau_desc_16 {
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struct aau_desc_16 *d_next; /* pointer to next (va) */
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uint32_t d_pa; /* our physical address */
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/* Hardware portion -- must be 32-byte aligned. */
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uint32_t d_nda; /* next descriptor address */
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uint32_t d_sar[4]; /* source address */
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uint32_t d_dar; /* destination address */
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uint32_t d_bc; /* byte count */
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uint32_t d_dc; /* descriptor control */
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/* Mini Descriptor */
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uint32_t d_sar5_8[4]; /* source address */
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/* Extended Descriptor 0 */
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uint32_t d_edc0; /* ext. descriptor control */
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uint32_t d_sar9_16[8]; /* source address */
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} __attribute__((__packed__));
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struct aau_desc_32 {
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struct aau_desc_32 *d_next; /* pointer to next (va) */
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uint32_t d_pa; /* our physical address */
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/* Hardware portion -- must be 32-byte aligned. */
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uint32_t d_nda; /* next descriptor address */
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uint32_t d_sar[4]; /* source address */
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uint32_t d_dar; /* destination address */
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uint32_t d_bc; /* byte count */
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uint32_t d_dc; /* descriptor control */
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/* Mini Descriptor */
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uint32_t d_sar5_8[4]; /* source address */
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/* Extended Descriptor 0 */
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uint32_t d_edc0; /* ext. descriptor control */
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uint32_t d_sar9_16[8]; /* source address */
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/* Extended Descriptor 1 */
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uint32_t d_edc1; /* ext. descriptor control */
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uint32_t d_sar17_24[8]; /* source address */
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/* Extended Descriptor 2 */
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uint32_t d_edc2; /* ext. descriptor control */
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uint32_t d_sar25_32[8]; /* source address */
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} __attribute__((__packed__));
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#define AAU_DESC_SIZE(ninputs) \
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((ninputs > 16) ? sizeof(struct aau_desc_32) : \
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(ninputs > 8) ? sizeof(struct aau_desc_16) : \
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(ninputs > 4) ? sizeof(struct aau_desc_8) : \
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sizeof(struct aau_desc_4))
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#define SYNC_DESC_4_OFFSET offsetof(struct aau_desc_4, d_nda)
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#define SYNC_DESC_4_SIZE (sizeof(struct aau_desc_4) - SYNC_DESC_4_OFFSET)
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#define SYNC_DESC(d, size) \
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cpu_dcache_wbinv_range(((vaddr_t)(d)) + SYNC_DESC_4_OFFSET, (size))
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/* Descriptor control */
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#define AAU_DC_IE (1U << 0) /* interrupt enable */
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#define AAU_DC_B1_CC(x) ((x) << 1) /* block command/control */
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#define AAU_DC_B2_CC(x) ((x) << 4)
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#define AAU_DC_B3_CC(x) ((x) << 7)
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#define AAU_DC_B4_CC(x) ((x) << 10)
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#define AAU_DC_B5_CC(x) ((x) << 13)
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#define AAU_DC_B6_CC(x) ((x) << 16)
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#define AAU_DC_B7_CC(x) ((x) << 19)
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#define AAU_DC_B8_CC(x) ((x) << 22)
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#define AAU_DC_SBCI_5_8 (1U << 25) /* SAR5-SAR8 valid */
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#define AAU_DC_SBCI_5_16 (2U << 25) /* SAR5-SAR16 valid */
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#define AAU_DC_SBCI_5_32 (3U << 25) /* SAR5-SAR32 valid */
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#define AAU_DC_TC (1U << 28) /* transfer complete */
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#define AAU_DC_PERR (1U << 29) /* parity check error */
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#define AAU_DC_PENB (1U << 30) /* parity check enable */
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#define AAU_DC_DWE (1U << 31) /* destination write enable */
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#define AAU_DC_CC_NULL 0 /* null command */
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#define AAU_DC_CC_XOR 1U /* XOR command */
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#define AAU_DC_CC_FILL 2U /* fill command */
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#define AAU_DC_CC_DIRECT_FILL 7U /* direct fill (copy) */
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/* Extended descriptor control */
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#define AAU_EDC_B1_CC(x) ((x) << 1) /* block command/control */
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#define AAU_EDC_B2_CC(x) ((x) << 4) /* block command/control */
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#define AAU_EDC_B3_CC(x) ((x) << 7) /* block command/control */
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#define AAU_EDC_B4_CC(x) ((x) << 10) /* block command/control */
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#define AAU_EDC_B5_CC(x) ((x) << 13) /* block command/control */
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#define AAU_EDC_B6_CC(x) ((x) << 16) /* block command/control */
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#define AAU_EDC_B7_CC(x) ((x) << 19) /* block command/control */
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#define AAU_EDC_B8_CC(x) ((x) << 22) /* block command/control */
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/* Hardware registers */
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#define AAU_ACR 0x00 /* accelerator control */
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#define AAU_ASR 0x04 /* accelerator status */
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#define AAU_ADAR 0x08 /* descriptor address */
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#define AAU_ANDAR 0x0c /* next descriptor address */
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#define AAU_DAR 0x20 /* destination address */
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#define AAU_ABCR 0x24 /* byte count */
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#define AAU_ADCR 0x28 /* descriptor control */
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/* i80321 only */
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#define AAU_EDCR0 0x3c /* extended descriptor control 0 */
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#define AAU_EDCR1 0x60 /* extended descriptor control 1 */
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#define AAU_EDCR2 0x84 /* extended descriptor control 2 */
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#define AAU_ACR_AAE (1U << 0) /* accelerator enable */
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#define AAU_ACR_CR (1U << 1) /* chain resume */
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#define AAU_ACR_512 (1U << 2) /* 512-byte buffer enable */
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#define AAU_ASR_MA (1U << 5) /* master abort */
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#define AAU_ASR_ECIF (1U << 8) /* end of chain interrupt */
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#define AAU_ASR_ETIF (1U << 9) /* end of transfer interrupt */
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#define AAU_ASR_AAF (1U << 10) /* acellerator active */
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#define AAU_ABCR_MASK 0x00ffffff /* 24-bit count */
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#endif /* _XSCALE_IOPAAUREG_H_ */
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