449902fc06
the eeprom on common types of memory modules. The specifications are displayed during boot and can later be queried in the hw.spdmemN sysctl subtree. Stub driver written by Nicolas Joly and greatly improved upon by Paul Goyette. From PR 36745, with additional improvements by Paul and me.
418 lines
10 KiB
C
418 lines
10 KiB
C
/* $NetBSD: spdmemvar.h,v 1.1 2007/08/18 11:26:37 tnn Exp $ */
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/*
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* Copyright (c) 2007 Paul Goyette
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* Copyright (c) 2007 Tobias Nygren
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#if BYTE_ORDER == BIG_ENDIAN
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#define SPD_BITFIELD(a, b, c, d) d; c; b; a
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#else
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#define SPD_BITFIELD(a, b, c, d) a; b; c; d
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#endif
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struct spdmem_fpm { /* FPM and EDO DIMMS */
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uint8_t fpm_rows;
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uint8_t fpm_cols;
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uint8_t fpm_banks;
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uint16_t fpm_datawidth; /* endian-sensitive */
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uint8_t fpm_voltage;
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uint8_t fpm_tRAC;
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uint8_t fpm_tCAC;
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uint8_t fpm_config;
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SPD_BITFIELD( \
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uint8_t fpm_refresh:7, \
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uint8_t fpm_selfrefresh:1, , \
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);
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uint8_t fpm_dram_dramwidth;
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uint8_t fpm_dram_eccwidth;
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uint8_t fpm_unused2[17];
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uint8_t fpm_superset;
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uint8_t fpm_unused3[30];
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} __attribute__((__packed__));
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struct spdmem_sdram { /* PC66/PC100/PC133 SDRAM */
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SPD_BITFIELD( \
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uint8_t sdr_rows:4, \
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uint8_t sdr_rows2:4, , \
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);
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SPD_BITFIELD( \
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uint8_t sdr_cols:4, \
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uint8_t sdr_cols2:4, , \
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);
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uint8_t sdr_banks;
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uint16_t sdr_datawidth; /* endian-sensitive */
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uint8_t sdr_voltage;
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SPD_BITFIELD( \
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uint8_t sdr_cycle_tenths:4, \
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uint8_t sdr_cycle_whole:4, , \
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);
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SPD_BITFIELD(
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uint8_t sdr_tAC_tenths:4, \
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uint8_t sdr_tAC_whole:4, , \
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);
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uint8_t sdr_config;
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SPD_BITFIELD( \
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uint8_t sdr_refresh:7, \
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uint8_t sdr_selfrefresh:1, , \
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);
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SPD_BITFIELD( \
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uint8_t sdr_dramwidth:7, \
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uint8_t sdr_dram_asym_bank2:1, ,\
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);
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SPD_BITFIELD( \
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uint8_t sdr_eccwidth:7, \
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uint8_t sdr_ecc_asym_bank2:1, , \
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);
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uint8_t sdr_min_clk_delay;
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SPD_BITFIELD( \
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uint8_t sdr_burstlengths:4, \
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uint8_t sdr_unused1:4, , \
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);
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uint8_t sdr_banks_per_chip;
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uint8_t sdr_tCAS;
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uint8_t sdr_tCS;
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uint8_t sdr_tWE;
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uint8_t sdr_mod_attrs;
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uint8_t sdr_dev_attrs;
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uint8_t sdr_min_cc_1;
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uint8_t sdr_max_tAC_1;
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uint8_t sdr_min_cc_2;
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uint8_t sdr_max_tAC_2;
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uint8_t sdr_tRP;
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uint8_t sdr_tRRD;
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uint8_t sdr_tRCD;
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uint8_t sdr_tRAS;
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uint8_t sdr_module_rank_density;
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uint8_t sdr_tIS;
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#define sdr_superset sdr_tIS
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uint8_t sdr_tIH;
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uint8_t sdr_tDS;
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uint8_t sdr_tDH;
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uint8_t sdr_unused2[5];
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uint8_t sdr_tRC;
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uint8_t sdr_unused3[20];
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uint8_t sdr_esdram;
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uint8_t sdr_super_tech;
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uint8_t sdr_spdrev;
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} __attribute__((__packed__));
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struct spdmem_rom {
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uint8_t rom_rows;
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uint8_t rom_cols;
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uint8_t rom_banks;
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uint16_t rom_datawidth; /* endian-sensitive */
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uint8_t rom_voltage;
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uint16_t rom_tAA; /* endian-sensitive */
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uint8_t rom_config;
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uint8_t rom_unused1;
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uint8_t rom_tPA;
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uint8_t rom_tOE;
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uint16_t rom_tCE; /* endian-sensitive */
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uint8_t rom_burstlength;
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uint8_t rom_unused2[14];
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uint8_t rom_superset[31];
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} __attribute__((__packed__));
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struct spdmem_ddr { /* Dual Data Rate SDRAM */
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SPD_BITFIELD( \
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uint8_t ddr_rows:4, \
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uint8_t ddr_rows2:4, , \
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);
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SPD_BITFIELD( \
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uint8_t ddr_cols:4, \
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uint8_t ddr_cols2:4, , \
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);
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uint8_t ddr_ranks;
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uint16_t ddr_datawidth; /* endian-sensitive */
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uint8_t ddr_voltage;
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SPD_BITFIELD( \
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uint8_t ddr_cycle_tenths:4, \
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uint8_t ddr_cycle_whole:4, , \
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);
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SPD_BITFIELD( \
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uint8_t ddr_tAC_hundredths:4, \
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uint8_t ddr_tAC_tenths:4, , \
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);
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uint8_t ddr_config;
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SPD_BITFIELD( \
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uint8_t ddr_refresh:7, \
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uint8_t ddr_selfrefresh:1, , \
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);
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SPD_BITFIELD( \
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uint8_t ddr_dramwidth:7, \
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uint8_t ddr_dram_asym_bank2:1, ,\
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);
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SPD_BITFIELD( \
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uint8_t ddr_eccwidth:7, \
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uint8_t ddr_ecc_asym_bank2:1, , \
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);
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uint8_t ddr_min_clk_delay;
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SPD_BITFIELD( \
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uint8_t ddr_burstlengths:4, \
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uint8_t ddr_unused1:4, , \
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);
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uint8_t ddr_banks_per_chip;
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uint8_t ddr_tCAS;
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uint8_t ddr_tCS;
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uint8_t ddr_tWE;
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uint8_t ddr_mod_attrs;
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uint8_t ddr_dev_attrs;
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uint8_t ddr_min_cc_05;
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uint8_t ddr_max_tAC_05;
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uint8_t ddr_min_cc_1;
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uint8_t ddr_max_tAC_1;
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uint8_t ddr_tRP;
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uint8_t ddr_tRRD;
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uint8_t ddr_tRCD;
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uint8_t ddr_tRAS;
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uint8_t ddr_module_rank_density;
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uint8_t ddr_tIS;
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#define ddr_superset ddr_tIS
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uint8_t ddr_tIH;
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uint8_t ddr_tDS;
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uint8_t ddr_tDH;
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uint8_t ddr_unused2[5];
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uint8_t ddr_tRC;
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uint8_t ddr_tRFC;
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uint8_t ddr_tCK;
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uint8_t ddr_tDQSQ;
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uint8_t ddr_tQHS;
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uint8_t ddr_unused3;
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uint8_t ddr_height;
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uint8_t ddr_unused4[15];
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} __attribute__((__packed__));
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struct spdmem_ddr2 { /* Dual Data Rate 2 SDRAM */
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SPD_BITFIELD( \
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uint8_t ddr2_rows:5, \
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uint8_t ddr2_unused1:3, , \
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);
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SPD_BITFIELD( \
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uint8_t ddr2_cols:4, \
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uint8_t ddr2_unused2:4, , \
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);
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SPD_BITFIELD( \
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uint8_t ddr2_ranks:3,
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uint8_t ddr2_cardoncard:1, \
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uint8_t ddr2_package:1, \
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uint8_t ddr2_height:3 \
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);
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uint8_t ddr2_datawidth;
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uint8_t ddr2_unused3;
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uint8_t ddr2_voltage;
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SPD_BITFIELD( \
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uint8_t ddr2_cycle_frac:4, \
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uint8_t ddr2_cycle_whole:4, , \
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);
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SPD_BITFIELD( \
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uint8_t ddr2_tAC_hundredths:4, \
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uint8_t ddr2_tAC_tenths:4, , \
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);
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uint8_t ddr2_config;
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SPD_BITFIELD( \
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uint8_t ddr2_refresh:7, \
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uint8_t ddr2_selfrefresh:1, , \
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);
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uint8_t ddr2_dramwidth;
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uint8_t ddr2_eccwidth;
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uint8_t ddr2_unused4;
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SPD_BITFIELD( \
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uint8_t ddr2_burstlengths:4, \
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uint8_t ddr2_unused5:4, , \
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);
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uint8_t ddr2_banks_per_chip;
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uint8_t ddr2_tCAS;
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uint8_t ddr2_mechanical;
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uint8_t ddr2_dimm_type;
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uint8_t ddr2_mod_attrs;
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uint8_t ddr2_dev_attrs;
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uint8_t ddr2_min_cc_1;
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uint8_t ddr2_max_tAC_1;
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uint8_t ddr2_min_cc_2;
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uint8_t ddr2_max_tAC_2;
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uint8_t ddr2_tRP;
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uint8_t ddr2_tRRD;
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uint8_t ddr2_tRCD;
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uint8_t ddr2_tRAS;
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uint8_t ddr2_module_rank_density;
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uint8_t ddr2_tIS;
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uint8_t ddr2_tIH;
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uint8_t ddr2_tDS;
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uint8_t ddr2_tDH;
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uint8_t ddr2_tWR;
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uint8_t ddr2_tWTR;
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uint8_t ddr2_tRTP;
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uint8_t ddr2_probe;
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uint8_t ddr2_extensions;
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uint8_t ddr2_tRC;
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uint8_t ddr2_tRFC;
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uint8_t ddr2_tCK;
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uint8_t ddr2_tDQSQ;
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uint8_t ddr2_tQHS;
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uint8_t ddr2_pll_relock;
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uint8_t ddr2_Tcasemax;
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uint8_t ddr2_Psi_TA_DRAM;
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uint8_t ddr2_dt0;
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uint8_t ddr2_dt2NQ;
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uint8_t ddr2_dr2P;
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uint8_t ddr2_dt3N;
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uint8_t ddr2_dt3Pfast;
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uint8_t ddr2_dt3Pslow;
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uint8_t ddr2_dt4R_4R4W_mode;
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uint8_t ddr2_dt5B;
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uint8_t ddr2_dt7;
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uint8_t ddr2_Psi_TA_PLL;
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uint8_t ddr2_Psi_TA_Reg;
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uint8_t ddr2_dt_PLL_Active;
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uint8_t ddr2_dt_Reg_Active;
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uint8_t ddr2_spdrev;
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} __attribute__((__packed__));
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struct spdmem_fbdimm { /* Fully-buffered DIMM */
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SPD_BITFIELD( \
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uint8_t fbdimm_ps1_voltage:4, \
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uint8_t fbdimm_ps2_voltage:4, , \
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);
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SPD_BITFIELD( \
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uint8_t fbdimm_banks:2, \
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uint8_t fbdimm_cols:3, \
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uint8_t fbdimm_rows:3, \
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);
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SPD_BITFIELD( \
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uint8_t fbdimm_thick:3, \
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uint8_t fbdimm_height:3, \
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uint8_t fbdimm_unused1:2, \
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);
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uint8_t fbdimm_mod_type;
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SPD_BITFIELD( \
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uint8_t fbdimm_dev_width:3, \
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uint8_t fbdimm_ranks:3, \
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uint8_t fbdimm_unused2:2, \
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);
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SPD_BITFIELD( \
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uint8_t fbdimm_ftb_divisor:4, \
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uint8_t fbdimm_ftp_dividend:4, ,\
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);
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uint8_t fbdimm_mtb_dividend;
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uint8_t fbdimm_mtb_divisor;
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uint8_t fbdimm_cycle_min;
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uint8_t fbdimm_cycle_max;
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uint8_t fbdimm_tCAS;
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uint8_t fbdimm_tAA_min;
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SPD_BITFIELD( \
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uint8_t fbdimm_tWR_min:4, \
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uint8_t fbdimm_WR_range:4, , \
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);
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uint8_t fbdimm_tWR;
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SPD_BITFIELD( \
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uint8_t fbdimm_tWL_min:4, \
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uint8_t fbdimm_tWL_range:4, , \
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);
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SPD_BITFIELD( \
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uint8_t fbdimm_tAL_min:4, \
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uint8_t fbdimm_tAL_range:4, , \
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);
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uint8_t fbdimm_tRCD;
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uint8_t fbdimm_tRRD;
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uint8_t fbdimm_tRP;
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SPD_BITFIELD( \
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uint8_t fbdimm_tRAS_high:4, \
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uint8_t fbdimm_tRC_high:4, , \
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);
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uint8_t fbdimm_tRAS_lo;
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uint8_t fbdimm_tRC_lo;
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uint16_t fbdimm_tRFC; /* endian-sensitive */
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uint8_t fbdimm_tWTR;
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uint8_t fbdimm_tRTP;
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SPD_BITFIELD( \
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uint8_t fbdimm_burst_4:1, \
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uint8_t fbdimm_burst_8:1, \
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uint8_t fbdimm_unused3:6, \
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);
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uint8_t fbdimm_terms;
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uint8_t fbdimm_drivers;
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uint8_t fbdimm_tREFI;
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uint8_t fbdimm_Tcasemax;
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uint8_t fbdimm_Psi_TA_SDRAM;
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uint8_t fbdimm_DT0;
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uint8_t fbdimm_DT2N_DT2Q;
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uint8_t fbdimm_DT2P;
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uint8_t fbdimm_DT3N;
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uint8_t fbdimm_DT4R_DT4R4W;
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uint8_t fbdimm_DT5B;
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uint8_t fbdimm_DT7;
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uint8_t fbdimm_unused4[21];
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} __attribute__((__packed__));
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struct spdmem_rambus { /* Direct Rambus DRAM */
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SPD_BITFIELD( \
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uint8_t rdr_rows:4, \
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uint8_t rdr_cols:4, , \
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);
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} __attribute__((__packed__));
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struct spdmem {
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uint8_t sm_len;
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uint8_t sm_size;
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uint8_t sm_type;
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union {
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struct spdmem_fbdimm u1_fbd;
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struct spdmem_fpm u1_fpm;
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struct spdmem_ddr u1_ddr;
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struct spdmem_ddr2 u1_ddr2;
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struct spdmem_sdram u1_sdr;
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struct spdmem_rambus u1_rdr;
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struct spdmem_rom u1_rom;
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} sm_u1;
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#define sm_fbd sm_u1.u1_fbd
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#define sm_fpm sm_u1.u1_fpm
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#define sm_ddr sm_u1.u1_ddr
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#define sm_ddr2 sm_u1.u1_ddr2
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#define sm_rdr sm_u1.u1_rdr
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#define sm_rom sm_u1.u1_rom
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#define sm_sdr sm_u1.u1_sdr
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uint8_t sm_cksum;
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} __attribute__((__packed__));
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/* some fields are in the same place for all memory types */
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#define sm_config sm_fpm.fpm_config
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#define sm_voltage sm_fpm.fpm_voltage
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#define sm_refresh sm_fpm.fpm_refresh
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#define sm_selfrefresh sm_fpm.fpm_selfrefresh
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#define SPDMEM_TYPE_MAXLEN 16
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struct spdmem_softc {
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struct device sc_dev;
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i2c_tag_t sc_tag;
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i2c_addr_t sc_addr;
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struct spdmem sc_spd_data;
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char sc_type[SPDMEM_TYPE_MAXLEN];
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};
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