383 lines
11 KiB
C
383 lines
11 KiB
C
/* $NetBSD: svwsata.c,v 1.24 2018/12/09 11:14:02 jdolecek Exp $ */
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/*
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* Copyright (c) 2005 Mark Kettenis
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: svwsata.c,v 1.24 2018/12/09 11:14:02 jdolecek Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <dev/ata/atareg.h>
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#include <dev/ata/satareg.h>
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#include <dev/ata/satavar.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciidereg.h>
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#include <dev/pci/pciidevar.h>
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#include <dev/pci/pciide_svwsata_reg.h>
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static int svwsata_match(device_t, cfdata_t, void *);
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static void svwsata_attach(device_t, device_t, void *);
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static void svwsata_chip_map(struct pciide_softc *,
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const struct pci_attach_args *);
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static void svwsata_mapreg_dma(struct pciide_softc *,
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const struct pci_attach_args *);
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static void svwsata_mapchan(struct pciide_channel *);
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int svwsata_intr(void *);
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CFATTACH_DECL_NEW(svwsata, sizeof(struct pciide_softc),
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svwsata_match, svwsata_attach, pciide_detach, NULL);
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static const struct pciide_product_desc pciide_svwsata_products[] = {
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{ PCI_PRODUCT_SERVERWORKS_K2_SATA,
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0,
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"ServerWorks K2 SATA Controller",
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svwsata_chip_map
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},
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{ PCI_PRODUCT_SERVERWORKS_FRODO4_SATA,
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0,
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"ServerWorks Frodo4 SATA Controller",
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svwsata_chip_map
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},
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{ PCI_PRODUCT_SERVERWORKS_FRODO8_SATA,
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0,
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"ServerWorks Frodo8 SATA Controller",
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svwsata_chip_map
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},
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{ PCI_PRODUCT_SERVERWORKS_HT1000_SATA_1,
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0,
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"ServerWorks HT-1000 SATA Controller",
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svwsata_chip_map
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},
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{ PCI_PRODUCT_SERVERWORKS_HT1000_SATA_2,
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0,
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"ServerWorks HT-1000 SATA Controller",
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svwsata_chip_map
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},
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{ 0,
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0,
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NULL,
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NULL,
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}
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};
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static int
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svwsata_match(device_t parent, cfdata_t match, void *aux)
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{
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struct pci_attach_args *pa = aux;
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SERVERWORKS) {
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if (pciide_lookup_product(pa->pa_id,
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pciide_svwsata_products))
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return (2);
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}
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return (0);
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}
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static void
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svwsata_attach(device_t parent, device_t self, void *aux)
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{
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struct pci_attach_args *pa = aux;
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struct pciide_softc *sc = device_private(self);
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sc->sc_wdcdev.sc_atac.atac_dev = self;
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pciide_common_attach(sc, pa,
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pciide_lookup_product(pa->pa_id, pciide_svwsata_products));
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}
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static void
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svwsata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
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{
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struct pciide_channel *cp;
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pci_intr_handle_t intrhandle;
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pcireg_t interface;
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const char *intrstr;
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int channel;
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char intrbuf[PCI_INTRSTR_LEN];
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/* The 4-port version has a dummy second function. */
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if (pci_conf_read(sc->sc_pc, sc->sc_tag,
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PCI_MAPREG_START + 0x14) == 0) {
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aprint_normal("\n");
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return;
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}
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if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
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PCI_MAPREG_TYPE_MEM |
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PCI_MAPREG_MEM_TYPE_32BIT, 0,
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&sc->sc_ba5_st, &sc->sc_ba5_sh,
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NULL, &sc->sc_ba5_ss) != 0) {
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aprint_error(": unable to map BA5 register space\n");
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return;
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}
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aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
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"bus-master DMA support present");
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svwsata_mapreg_dma(sc, pa);
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aprint_verbose("\n");
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sc->sc_wdcdev.cap = WDC_CAPABILITY_WIDEREGS;
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
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sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
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if (sc->sc_dma_ok) {
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
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sc->sc_wdcdev.irqack = pciide_irqack;
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sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
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sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
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}
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sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
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sc->sc_wdcdev.sc_atac.atac_nchannels = 4;
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sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
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/* We can use SControl and SStatus to probe for drives. */
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sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe;
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sc->sc_wdcdev.wdc_maxdrives = 1;
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wdc_allocate_regs(&sc->sc_wdcdev);
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/* Map and establish the interrupt handler. */
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if(pci_intr_map(pa, &intrhandle) != 0) {
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aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
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"couldn't map native-PCI interrupt\n");
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return;
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}
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intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf));
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sc->sc_pci_ih = pci_intr_establish_xname(pa->pa_pc, intrhandle, IPL_BIO,
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svwsata_intr, sc, device_xname(sc->sc_wdcdev.sc_atac.atac_dev));
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if (sc->sc_pci_ih != NULL) {
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aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
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"using %s for native-PCI interrupt\n",
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intrstr ? intrstr : "unknown interrupt");
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} else {
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aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
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"couldn't establish native-PCI interrupt");
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if (intrstr != NULL)
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aprint_error(" at %s", intrstr);
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aprint_error("\n");
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return;
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}
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interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
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PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
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for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
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channel++) {
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cp = &sc->pciide_channels[channel];
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if (pciide_chansetup(sc, channel, interface) == 0)
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continue;
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svwsata_mapchan(cp);
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}
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}
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static void
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svwsata_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa)
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{
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struct pciide_channel *pc;
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int chan, reg;
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bus_size_t size;
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sc->sc_wdcdev.dma_arg = sc;
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sc->sc_wdcdev.dma_init = pciide_dma_init;
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sc->sc_wdcdev.dma_start = pciide_dma_start;
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sc->sc_wdcdev.dma_finish = pciide_dma_finish;
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if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
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PCIIDE_OPTIONS_NODMA) {
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aprint_normal(
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", but unused (forced off by config file)");
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sc->sc_dma_ok = 0;
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return;
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}
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/*
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* Slice off a subregion of BA5 for each of the channel's DMA
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* registers.
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*/
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sc->sc_dma_iot = sc->sc_ba5_st;
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for (chan = 0; chan < 4; chan++) {
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pc = &sc->pciide_channels[chan];
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for (reg = 0; reg < IDEDMA_NREGS; reg++) {
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size = 4;
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if (size > (IDEDMA_SCH_OFFSET - reg))
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size = IDEDMA_SCH_OFFSET - reg;
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if (bus_space_subregion(sc->sc_ba5_st,
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sc->sc_ba5_sh,
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(chan << 8) + SVWSATA_DMA + reg,
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size, &pc->dma_iohs[reg]) != 0) {
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sc->sc_dma_ok = 0;
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aprint_normal(", but can't subregion offset "
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"%lu size %lu",
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(u_long) (chan << 8) + SVWSATA_DMA + reg,
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(u_long) size);
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return;
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}
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}
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}
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/* DMA registers all set up! */
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sc->sc_dmat = pa->pa_dmat;
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sc->sc_dma_ok = 1;
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}
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static void
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svwsata_mapchan(struct pciide_channel *cp)
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{
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struct ata_channel *wdc_cp = &cp->ata_channel;
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struct pciide_softc *sc = CHAN_TO_PCIIDE(wdc_cp);
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struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp);
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int i;
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cp->compat = 0;
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cp->ih = sc->sc_pci_ih;
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wdr->cmd_iot = sc->sc_ba5_st;
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if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
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(wdc_cp->ch_channel << 8) + SVWSATA_TF0,
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SVWSATA_TF8 - SVWSATA_TF0, &wdr->cmd_baseioh) != 0) {
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aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
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"couldn't map %s cmd regs\n", cp->name);
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goto bad;
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}
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wdr->ctl_iot = sc->sc_ba5_st;
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if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
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(wdc_cp->ch_channel << 8) + SVWSATA_TF8, 4,
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&cp->ctl_baseioh) != 0) {
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aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
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"couldn't map %s ctl regs\n", cp->name);
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goto bad;
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}
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wdr->ctl_ioh = cp->ctl_baseioh;
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for (i = 0; i < WDC_NREG; i++) {
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if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
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i << 2, i == 0 ? 4 : 1,
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&wdr->cmd_iohs[i]) != 0) {
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aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
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"couldn't subregion %s channel cmd regs\n",
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cp->name);
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goto bad;
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}
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}
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wdc_init_shadow_regs(wdr);
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wdr->data32iot = wdr->cmd_iot;
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wdr->data32ioh = wdr->cmd_iohs[0];
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wdr->sata_iot = sc->sc_ba5_st;
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wdr->sata_baseioh = sc->sc_ba5_sh;
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if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
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(wdc_cp->ch_channel << 8) + SVWSATA_SSTATUS, 1,
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&wdr->sata_status) != 0) {
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aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
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"couldn't map channel %d sata_status regs\n",
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wdc_cp->ch_channel);
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goto bad;
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}
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if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
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(wdc_cp->ch_channel << 8) + SVWSATA_SERROR, 1,
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&wdr->sata_error) != 0) {
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aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
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"couldn't map channel %d sata_error regs\n",
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wdc_cp->ch_channel);
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goto bad;
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}
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if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
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(wdc_cp->ch_channel << 8) + SVWSATA_SCONTROL, 1,
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&wdr->sata_control) != 0) {
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aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
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"couldn't map channel %d sata_control regs\n",
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wdc_cp->ch_channel);
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goto bad;
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}
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bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh,
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(wdc_cp->ch_channel << 8) + SVWSATA_SICR1,
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bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh,
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(wdc_cp->ch_channel << 8) + SVWSATA_SICR1)
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& ~0x00040000);
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bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh,
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(wdc_cp->ch_channel << 8) + SVWSATA_SERROR, 0xffffffff);
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bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh,
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(wdc_cp->ch_channel << 8) + SVWSATA_SIM, 0);
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cp->ata_channel.ch_flags |= ATACH_DMA_BEFORE_CMD;
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wdcattach(wdc_cp);
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return;
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bad:
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cp->ata_channel.ch_flags |= ATACH_DISABLED;
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}
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int
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svwsata_intr(void *arg)
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{
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struct pciide_softc *sc = arg;
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struct pciide_channel *cp;
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struct ata_channel *wdc_cp;
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struct wdc_regs *wdr;
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int i, rv, crv;
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uint8_t dmastat;
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rv = 0;
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for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
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volatile uint32_t status;
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cp = &sc->pciide_channels[i];
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wdc_cp = &cp->ata_channel;
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wdr = CHAN_TO_WDC_REGS(wdc_cp);
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/*
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* from FreeBSD's ata-serverworks.c:
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* We need to do a 4-byte read on the status reg before the
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* values will report correctly
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*/
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bus_space_read_4(wdr->cmd_iot,
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wdr->cmd_iohs[wd_status], 0);
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__USE(status);
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dmastat = bus_space_read_1(sc->sc_dma_iot,
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cp->dma_iohs[IDEDMA_CTL], 0);
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/* If a compat channel skip. */
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if (cp->compat)
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continue;
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/* if this channel not waiting for intr, skip */
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if ((wdc_cp->ch_flags & ATACH_IRQ_WAIT) == 0) {
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continue;
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}
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crv = wdcintr(wdc_cp);
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if (crv == 0) {
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bus_space_write_1(sc->sc_dma_iot,
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cp->dma_iohs[IDEDMA_CTL], 0, dmastat);
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}
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else if (crv == 1)
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rv = 1; /* claim the intr */
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else if (rv == 0) /* crv should be -1 in this case */
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rv = crv; /* if we've done no better, take it */
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}
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return (rv);
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}
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