182 lines
6.1 KiB
C
182 lines
6.1 KiB
C
/* $NetBSD: pciide_opti_reg.h,v 1.12 2008/04/28 20:23:55 martin Exp $ */
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/*-
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Steve C. Woodford.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Register definitions for OPTi PCIIDE controllers based on
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* their 82c621 chip.
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*/
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/* IDE Initialization Control Register */
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#define OPTI_REG_INIT_CONTROL 0x40
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#define OPTI_INIT_CONTROL_MODE_PIO_0 0
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#define OPTI_INIT_CONTROL_MODE_PIO_1 2
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#define OPTI_INIT_CONTROL_MODE_PIO_2 1
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#define OPTI_INIT_CONTROL_MODE_PIO_3 3
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#define OPTI_INIT_CONTROL_ADDR_RELOC (1u << 2)
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#define OPTI_INIT_CONTROL_CH2_ENABLE 0
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#define OPTI_INIT_CONTROL_CH2_DISABLE (1u << 3)
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#define OPTI_INIT_CONTROL_FIFO_16 0
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#define OPTI_INIT_CONTROL_FIFO_32 (1u << 5)
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#define OPTI_INIT_CONTROL_FIFO_REQ_32 0
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#define OPTI_INIT_CONTROL_FIFO_REQ_30 (1u << 6)
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#define OPTI_INIT_CONTROL_FIFO_REQ_28 (2u << 6)
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#define OPTI_INIT_CONTROL_FIFO_REQ_26 (3u << 6)
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/* IDE Enhanced Features Register */
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#define OPTI_REG_ENH_FEAT 0x42
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#define OPTI_ENH_FEAT_X111_ENABLE (1u << 1)
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#define OPTI_ENH_FEAT_CONCURRENT_MAST (1u << 2)
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#define OPTI_ENH_FEAT_PCI_INVALIDATE (1u << 3)
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#define OPTI_ENH_FEAT_IDE_CONCUR (1u << 4)
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#define OPTI_ENH_FEAT_SLAVE_FIFO_ISA (1u << 5)
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/* IDE Enhanced Mode Register */
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#define OPTI_REG_ENH_MODE 0x43
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#define OPTI_ENH_MODE_MASK(c,d) (3u << (((c) * 4) + ((d) * 2)))
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#define OPTI_ENH_MODE_USE_TIMING(c,d) 0
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#define OPTI_ENH_MODE(c,d,m) ((m) << (((c) * 4) + ((d) * 2)))
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/* Timing registers */
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#define OPTI_REG_READ_CYCLE_TIMING 0x00
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#define OPTI_REG_WRITE_CYCLE_TIMING 0x01
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#define OPTI_RECOVERY_TIME_SHIFT 0
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#define OPTI_PULSE_WIDTH_SHIFT 4
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/*
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* Control register.
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*/
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#define OPTI_REG_CONTROL 0x03
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#define OPTI_CONTROL_DISABLE 0x11
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#define OPTI_CONTROL_ENABLE 0x95
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/* Strap register */
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#define OPTI_REG_STRAP 0x05
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#define OPTI_STRAP_PCI_SPEED_MASK 0x1u
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#define OPTI_STRAP_PCI_33 0
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#define OPTI_STRAP_PCI_25 1
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/* Miscellaneous register */
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#define OPTI_REG_MISC 0x06
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#define OPTI_MISC_INDEX(d) ((unsigned)(d))
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#define OPTI_MISC_INDEX_MASK 0x01u
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#define OPTI_MISC_DELAY_MASK 0x07u
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#define OPTI_MISC_DELAY_SHIFT 1
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#define OPTI_MISC_ADDR_SETUP_MASK 0x3u
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#define OPTI_MISC_ADDR_SETUP_SHIFT 4
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#define OPTI_MISC_READ_PREFETCH_ENABLE (1u << 6)
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#define OPTI_MISC_ADDR_SETUP_MASK 0x3u
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#define OPTI_MISC_WRITE_MASK 0x7fu
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/*
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* Inline functions for accessing the timing registers of the
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* OPTi controller.
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*
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* These *MUST* disable interrupts as they need atomic access to
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* certain magic registers. Failure to adhere to this *will*
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* break things in subtle ways if the wdc registers are accessed
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* by an interrupt routine while this magic sequence is executing.
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*/
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static __inline u_int8_t __unused
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opti_read_config(struct ata_channel *chp, int reg)
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{
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struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp);
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u_int8_t rv;
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int s = splhigh();
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/* Two consecutive 16-bit reads from register #1 (0x1f1/0x171) */
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(void) bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0);
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(void) bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0);
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/* Followed by an 8-bit write of 0x3 to register #2 */
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bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, 0x03u);
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/* Now we can read the required register */
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rv = bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[reg], 0);
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/* Restore the real registers */
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bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, 0x83u);
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splx(s);
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return rv;
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}
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static __inline void __unused
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opti_write_config(struct ata_channel *chp, int reg, u_int8_t val)
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{
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struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp);
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int s = splhigh();
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/* Two consecutive 16-bit reads from register #1 (0x1f1/0x171) */
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(void) bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0);
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(void) bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0);
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/* Followed by an 8-bit write of 0x3 to register #2 */
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bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, 0x03u);
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/* Now we can write the required register */
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bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[reg], 0, val);
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/* Restore the real registers */
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bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, 0x83u);
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splx(s);
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}
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/*
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* These are the timing register values for the various IDE modes
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* supported by the OPTi chip. The first index of the two-dimensional
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* arrays is used for a 33MHz PCIbus, the second for a 25MHz PCIbus.
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*/
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static const u_int8_t opti_tim_cp[2][8] __unused = {
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/* Command Pulse */
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{5, 4, 3, 2, 2, 7, 2, 2},
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{4, 3, 2, 2, 1, 5, 2, 1}
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};
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static const u_int8_t opti_tim_rt[2][8] __unused = {
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/* Recovery Time */
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{9, 4, 0, 0, 0, 6, 0, 0},
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{6, 2, 0, 0, 0, 4, 0, 0}
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};
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static const u_int8_t opti_tim_as[2][8] __unused = {
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/* Address Setup */
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{2, 1, 1, 1, 0, 0, 0, 0},
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{1, 1, 0, 0, 0, 0, 0, 0}
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};
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static const u_int8_t opti_tim_em[8] __unused = {
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/* Enhanced Mode */
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0, 0, 0, 1, 2, 0, 1 ,2
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};
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