280 lines
8.4 KiB
C
280 lines
8.4 KiB
C
/* $OpenBSD: if_bwfm_pci.h,v 1.2 2018/01/05 23:30:16 patrick Exp $ */
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/*
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* Copyright (c) 2010-2016 Broadcom Corporation
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* Copyright (c) 2017 Patrick Wildt <patrick@blueri.se>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/* Registers */
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#define BWFM_PCI_BAR0_WINDOW 0x80
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#define BWFM_PCI_BAR0_REG_SIZE 0x1000
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#define BWFM_PCI_ARMCR4REG_BANKIDX 0x40
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#define BWFM_PCI_ARMCR4REG_BANKPDA 0x4C
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#define BWFM_PCI_PCIE2REG_INTMASK 0x24
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#define BWFM_PCI_PCIE2REG_MAILBOXINT 0x48
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#define BWFM_PCI_PCIE2REG_MAILBOXMASK 0x4C
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#define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_FN0_0 0x0100
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#define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_FN0_1 0x0200
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#define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H0_DB0 0x10000
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#define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H0_DB1 0x20000
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#define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H1_DB0 0x40000
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#define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H1_DB1 0x80000
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#define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H2_DB0 0x100000
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#define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H2_DB1 0x200000
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#define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H3_DB0 0x400000
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#define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H3_DB1 0x800000
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#define BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H_DB \
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(BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H0_DB0 | \
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BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H0_DB1 | \
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BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H1_DB0 | \
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BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H1_DB1 | \
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BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H2_DB0 | \
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BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H2_DB1 | \
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BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H3_DB0 | \
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BWFM_PCI_PCIE2REG_MAILBOXMASK_INT_D2H3_DB1)
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#define BWFM_PCI_PCIE2REG_CONFIGADDR 0x120
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#define BWFM_PCI_PCIE2REG_CONFIGDATA 0x124
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#define BWFM_PCI_PCIE2REG_H2D_MAILBOX 0x140
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#define BWFM_PCI_CFGREG_STATUS_CMD 0x004
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#define BWFM_PCI_CFGREG_PM_CSR 0x04C
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#define BWFM_PCI_CFGREG_MSI_CAP 0x058
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#define BWFM_PCI_CFGREG_MSI_ADDR_L 0x05C
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#define BWFM_PCI_CFGREG_MSI_ADDR_H 0x060
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#define BWFM_PCI_CFGREG_MSI_DATA 0x064
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#define BWFM_PCI_CFGREG_LINK_STATUS_CTRL 0x0BC
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#define BWFM_PCI_CFGREG_LINK_STATUS_CTRL_ASPM_ENAB 0x3
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#define BWFM_PCI_CFGREG_LINK_STATUS_CTRL2 0x0DC
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#define BWFM_PCI_CFGREG_RBAR_CTRL 0x228
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#define BWFM_PCI_CFGREG_PML1_SUB_CTRL1 0x248
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#define BWFM_PCI_CFGREG_REG_BAR2_CONFIG 0x4E0
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#define BWFM_PCI_CFGREG_REG_BAR3_CONFIG 0x4F4
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#define BWFM_RAMSIZE 0x6c
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#define BWFM_RAMSIZE_MAGIC 0x534d4152 /* SMAR */
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#define BWFM_SHARED_INFO 0x000
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#define BWFM_SHARED_INFO_MIN_VERSION 5
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#define BWFM_SHARED_INFO_MAX_VERSION 6
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#define BWFM_SHARED_INFO_VERSION_MASK 0x00FF
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#define BWFM_SHARED_INFO_DMA_INDEX 0x10000
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#define BWFM_SHARED_INFO_DMA_2B_IDX 0x100000
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#define BWFM_SHARED_CONSOLE_ADDR 0x14
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#define BWFM_SHARED_MAX_RXBUFPOST 0x22
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#define BWFM_SHARED_MAX_RXBUFPOST_DEFAULT 255
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#define BWFM_SHARED_RX_DATAOFFSET 0x24
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#define BWFM_SHARED_HTOD_MB_DATA_ADDR 0x28
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#define BWFM_SHARED_DTOH_MB_DATA_ADDR 0x2c
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#define BWFM_SHARED_RING_INFO_ADDR 0x30
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#define BWFM_SHARED_DMA_SCRATCH_LEN 0x34
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#define BWFM_SHARED_DMA_SCRATCH_ADDR_LOW 0x38
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#define BWFM_SHARED_DMA_SCRATCH_ADDR_HIGH 0x3c
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#define BWFM_SHARED_DMA_RINGUPD_LEN 0x40
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#define BWFM_SHARED_DMA_RINGUPD_ADDR_LOW 0x44
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#define BWFM_SHARED_DMA_RINGUPD_ADDR_HIGH 0x48
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#define BWFM_RING_MAX_ITEM 0x04
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#define BWFM_RING_LEN_ITEMS 0x06
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#define BWFM_RING_MEM_BASE_ADDR_LOW 0x08
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#define BWFM_RING_MEM_BASE_ADDR_HIGH 0x0c
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#define BWFM_RING_MEM_SZ 16
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#define BWFM_CONSOLE_BUFADDR 0x08
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#define BWFM_CONSOLE_BUFSIZE 0x0c
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#define BWFM_CONSOLE_WRITEIDX 0x10
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struct bwfm_pci_ringinfo {
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uint32_t ringmem;
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uint32_t h2d_w_idx_ptr;
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uint32_t h2d_r_idx_ptr;
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uint32_t d2h_w_idx_ptr;
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uint32_t d2h_r_idx_ptr;
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uint32_t h2d_w_idx_hostaddr_low;
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uint32_t h2d_w_idx_hostaddr_high;
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uint32_t h2d_r_idx_hostaddr_low;
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uint32_t h2d_r_idx_hostaddr_high;
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uint32_t d2h_w_idx_hostaddr_low;
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uint32_t d2h_w_idx_hostaddr_high;
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uint32_t d2h_r_idx_hostaddr_low;
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uint32_t d2h_r_idx_hostaddr_high;
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uint16_t max_flowrings;
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uint16_t max_submissionrings;
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uint16_t max_completionrings;
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};
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/* Msgbuf defines */
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#define MSGBUF_IOCTL_RESP_TIMEOUT 2000 /* msecs */
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#define MSGBUF_IOCTL_REQ_PKTID 0xFFFE
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#define MSGBUF_MAX_PKT_SIZE 2048
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#define MSGBUF_TYPE_GEN_STATUS 0x1
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#define MSGBUF_TYPE_RING_STATUS 0x2
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#define MSGBUF_TYPE_FLOW_RING_CREATE 0x3
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#define MSGBUF_TYPE_FLOW_RING_CREATE_CMPLT 0x4
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#define MSGBUF_TYPE_FLOW_RING_DELETE 0x5
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#define MSGBUF_TYPE_FLOW_RING_DELETE_CMPLT 0x6
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#define MSGBUF_TYPE_FLOW_RING_FLUSH 0x7
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#define MSGBUF_TYPE_FLOW_RING_FLUSH_CMPLT 0x8
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#define MSGBUF_TYPE_IOCTLPTR_REQ 0x9
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#define MSGBUF_TYPE_IOCTLPTR_REQ_ACK 0xA
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#define MSGBUF_TYPE_IOCTLRESP_BUF_POST 0xB
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#define MSGBUF_TYPE_IOCTL_CMPLT 0xC
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#define MSGBUF_TYPE_EVENT_BUF_POST 0xD
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#define MSGBUF_TYPE_WL_EVENT 0xE
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#define MSGBUF_TYPE_TX_POST 0xF
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#define MSGBUF_TYPE_TX_STATUS 0x10
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#define MSGBUF_TYPE_RXBUF_POST 0x11
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#define MSGBUF_TYPE_RX_CMPLT 0x12
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#define MSGBUF_TYPE_LPBK_DMAXFER 0x13
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#define MSGBUF_TYPE_LPBK_DMAXFER_CMPLT 0x14
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struct msgbuf_common_hdr {
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uint8_t msgtype;
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uint8_t ifidx;
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uint8_t flags;
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uint8_t rsvd0;
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uint32_t request_id;
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};
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struct msgbuf_buf_addr {
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uint32_t low_addr;
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uint32_t high_addr;
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};
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struct msgbuf_ioctl_req_hdr {
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struct msgbuf_common_hdr msg;
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uint32_t cmd;
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uint16_t trans_id;
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uint16_t input_buf_len;
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uint16_t output_buf_len;
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uint16_t rsvd0[3];
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struct msgbuf_buf_addr req_buf_addr;
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uint32_t rsvd1[2];
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};
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struct msgbuf_tx_msghdr {
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struct msgbuf_common_hdr msg;
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uint8_t txhdr[ETHER_HDR_LEN];
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uint8_t flags;
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#define BWFM_MSGBUF_PKT_FLAGS_FRAME_802_3 (1 << 0)
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#define BWFM_MSGBUF_PKT_FLAGS_PRIO_SHIFT 5
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uint8_t seg_cnt;
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struct msgbuf_buf_addr metadata_buf_addr;
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struct msgbuf_buf_addr data_buf_addr;
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uint16_t metadata_buf_len;
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uint16_t data_len;
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uint32_t rsvd0;
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};
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struct msgbuf_rx_bufpost {
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struct msgbuf_common_hdr msg;
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uint16_t metadata_buf_len;
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uint16_t data_buf_len;
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uint32_t rsvd0;
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struct msgbuf_buf_addr metadata_buf_addr;
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struct msgbuf_buf_addr data_buf_addr;
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};
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struct msgbuf_rx_ioctl_resp_or_event {
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struct msgbuf_common_hdr msg;
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uint16_t host_buf_len;
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uint16_t rsvd0[3];
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struct msgbuf_buf_addr host_buf_addr;
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uint32_t rsvd1[4];
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};
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struct msgbuf_completion_hdr {
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uint16_t status;
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uint16_t flow_ring_id;
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};
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struct msgbuf_rx_event {
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struct msgbuf_common_hdr msg;
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struct msgbuf_completion_hdr compl_hdr;
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uint16_t event_data_len;
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uint16_t seqnum;
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uint16_t rsvd0[4];
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};
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struct msgbuf_ioctl_resp_hdr {
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struct msgbuf_common_hdr msg;
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struct msgbuf_completion_hdr compl_hdr;
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uint16_t resp_len;
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uint16_t trans_id;
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uint32_t cmd;
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uint32_t rsvd0;
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};
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struct msgbuf_tx_status {
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struct msgbuf_common_hdr msg;
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struct msgbuf_completion_hdr compl_hdr;
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uint16_t metadata_len;
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uint16_t tx_status;
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};
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struct msgbuf_rx_complete {
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struct msgbuf_common_hdr msg;
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struct msgbuf_completion_hdr compl_hdr;
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uint16_t metadata_len;
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uint16_t data_len;
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uint16_t data_offset;
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uint16_t flags;
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uint32_t rx_status_0;
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uint32_t rx_status_1;
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uint32_t rsvd0;
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};
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struct msgbuf_tx_flowring_create_req {
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struct msgbuf_common_hdr msg;
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uint8_t da[ETHER_ADDR_LEN];
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uint8_t sa[ETHER_ADDR_LEN];
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uint8_t tid;
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uint8_t if_flags;
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uint16_t flow_ring_id;
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uint8_t tc;
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uint8_t priority;
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uint16_t int_vector;
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uint16_t max_items;
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uint16_t len_item;
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struct msgbuf_buf_addr flow_ring_addr;
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};
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struct msgbuf_tx_flowring_delete_req {
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struct msgbuf_common_hdr msg;
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uint16_t flow_ring_id;
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uint16_t reason;
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uint32_t rsvd0[7];
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};
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struct msgbuf_flowring_create_resp {
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struct msgbuf_common_hdr msg;
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struct msgbuf_completion_hdr compl_hdr;
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uint32_t rsvd0[3];
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};
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struct msgbuf_flowring_delete_resp {
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struct msgbuf_common_hdr msg;
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struct msgbuf_completion_hdr compl_hdr;
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uint32_t rsvd0[3];
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};
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struct msgbuf_flowring_flush_resp {
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struct msgbuf_common_hdr msg;
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struct msgbuf_completion_hdr compl_hdr;
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uint32_t rsvd0[3];
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};
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