283 lines
11 KiB
C
283 lines
11 KiB
C
/* $NetBSD: cemacreg.h,v 1.3 2015/08/24 18:51:37 rjs Exp $ */
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/*-
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* Copyright (c) 2015 Genetec Corporation. All rights reserved.
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* Written by Hashimoto Kenichi for Genetec Corporation.
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*
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* Copyright (c) 2007 Embedtronics Oy
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* All rights reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#ifndef _IF_CEMACREG_H_
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#define _IF_CEMACREG_H_
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/* Ethernet MAC (EMAC),
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* at91rm9200.pdf, page 573 */
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#define ETH_CTL 0x00U /* 0x00: Control Register */
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#define ETH_CFG 0x04U /* 0x04: Configuration Register */
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#define ETH_SR 0x08U /* 0x08: Status Register */
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#define ETH_TAR 0x0CU /* 0x0C: Transmit Address Register (at91rm9200 only) */
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#define ETH_TCR 0x10U /* 0x10: Transmit Control Register (at91rm9200 only) */
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#define ETH_TSR 0x14U /* 0x14: Transmit Status Register */
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#define ETH_RBQP 0x18U /* 0x18: Receive Buffer Queue Pointer */
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#define ETH_TBQP 0x1CU /* 0x1C: Transmit Buffer Queue Pointer */
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#define ETH_RSR 0x20U /* 0x20: Receive Status Register */
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#define ETH_ISR 0x24U /* 0x24: Interrupt Status Register */
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#define ETH_IER 0x28U /* 0x28: Interrupt Enable Register */
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#define ETH_IDR 0x2CU /* 0x2C: Interrupt Disable Register */
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#define ETH_IMR 0x30U /* 0x30: Interrupt Mask Register */
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#define ETH_MAN 0x34U /* 0x34: PHY Maintenance Register */
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#define ETH_FRA 0x40U /* 0x40: Frames Transmitted OK */
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#define ETH_SCOL 0x44U /* 0x44: Single Collision Frames */
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#define ETH_MCOL 0x48U /* 0x48: Multiple Collision Frames */
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#define ETH_OK 0x4CU /* 0x4C: Frames Received OK */
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#define ETH_SEQE 0x50U /* 0x50: Frame Check Sequence Errors */
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#define ETH_ALE 0x54U /* 0x54: Alignment Errors */
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#define ETH_DTE 0x58U /* 0x58: Deferred Transmission Frame */
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#define ETH_LCOL 0x5CU /* 0x5C: Late Collisions */
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#define ETH_ECOL 0x60U /* 0x60: Excessive Collisions */
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#define ETH_CSE 0x64U /* 0x64: Carrier Sense Errors */
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#define ETH_TUE 0x68U /* 0x68: Transmit Underrun Errors */
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#define ETH_CDE 0x6CU /* 0x6C: Code Errors */
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#define ETH_ELR 0x70U /* 0x70: Excessive Length Errors */
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#define ETH_RJB 0x74U /* 0x74: Receive Jabbers */
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#define ETH_USF 0x78U /* 0x78: Undersize Frames */
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#define ETH_SQEE 0x7CU /* 0x7C: SQE Test Errors */
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#define ETH_DRFC 0x80U /* 0x80: Discarded RX Frames */
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#define ETH_HSH 0x90U /* 0x90: Hash Address High */
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#define ETH_HSL 0x94U /* 0x94: Hash Address Low */
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#define ETH_SA1L 0x98U /* 0x98: Specific Address 1 Low */
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#define ETH_SA1H 0x9CU /* 0x9C: Specific Address 1 High */
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#define ETH_SA2L 0xA0U /* 0xA0: Specific Address 2 Low */
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#define ETH_SA2H 0xA4U /* 0xA4: Specific Address 2 High */
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#define ETH_SA3L 0xA8U /* 0xA8: Specific Address 3 Low */
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#define ETH_SA3H 0xACU /* 0xAC: Specific Address 3 High */
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#define ETH_SA4L 0xB0U /* 0xB0: Specific Address 4 Low */
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#define ETH_SA4H 0xB4U /* 0xB4: Specific Address 4 High */
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/*
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* Gigabit Ethernet Controller (GEM)
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* ug585-Zynq-7000-TRM.pdf
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*/
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#define GEM_USER_IO 0x000C
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#define GEM_DMA_CFG 0x0010 /* DMA Configuration */
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#define GEM_DMA_CFG_DISC_WHEN_NO_AHB __BIT(24)
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#define GEM_DMA_CFG_RX_BUF_SIZE __BITS(23, 16)
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#define GEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN __BIT(11)
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#define GEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL __BIT(10)
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#define GEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL __BITS(9, 8)
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#define GEM_DMA_CFG_AHB_ENDIAN_SWAP_PKT_EN __BIT(7)
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#define GEM_DMA_CFG_AHB_ENDIAN_SWAP_MGMT_EN __BIT(6)
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#define GEM_DMA_CFG_AHB_FIXED_BURST_LEN __BITS(4, 0)
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#define GEM_HSH 0x0080
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#define GEM_HSL 0x0084
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#define GEM_SA1L 0x0088
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#define GEM_SA1H 0x008C
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#define GEM_SA2L 0x0090
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#define GEM_SA2H 0x0094
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#define GEM_SA3L 0x0098
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#define GEM_SA3H 0x009C
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#define GEM_SA4L 0x0090
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#define GEM_SA4H 0x0094
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#define GEM_SCOL 0x0138
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#define GEM_MCOL 0x013C
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#define GEM_DCFG2 0x0284
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#define GEM_DCFG3 0x0288
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#define GEM_DCFG4 0x028C
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#define GEM_DCFG5 0x0290
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#define ETH_SIZE 0x1000
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/* Control Register bits: */
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#define GEM_CTL_ZEROPAUSETX __BIT(12)
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#define GEM_CTL_PAUSETX __BIT(11)
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#define GEM_CTL_HALTTX __BIT(10)
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#define GEM_CTL_STARTTX __BIT(9)
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#define ETH_CTL_BP 0x100U /* 1 = back pressure enabled */
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#define ETH_CTL_WES 0x080U /* 1 = statistics registers writeable */
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#define ETH_CTL_ISR 0x040U /* 1 = increment statistics registers */
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#define ETH_CTL_CSR 0x020U /* 1 = clear statistics registers */
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#define ETH_CTL_MPE 0x010U /* 1 = management port enabled */
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#define ETH_CTL_TE 0x008U /* 1 = transmit enable */
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#define ETH_CTL_RE 0x004U /* 1 = receive enable */
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#define ETH_CTL_LBL 0x002U /* 1 = local loopback enabled */
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#define ETH_CTL_LB 0x001U /* 1 = loopback signal is at high level */
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/* Configuration Register bits: */
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#define ETH_CFG_RMII 0x2000U /* 1 = enable RMII (Reduce MII) (AT91RM9200 only) */
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#define ETH_CFG_RTY 0x1000U /* 1 = retry test enabled */
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#define ETH_CFG_CLK 0x0C00U /* clock */
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#define ETH_CFG_CLK_8 0x0000U
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#define ETH_CFG_CLK_16 0x0400U
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#define ETH_CFG_CLK_32 0x0800U
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#define ETH_CFG_CLK_64 0x0C00U
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#define ETH_CFG_EAE 0x0200U /* 1 = external address match enable */
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#define ETH_CFG_BIG 0x0100U /* 1 = receive up to 1522 bytes (VLAN) */
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#define ETH_CFG_UNI 0x0080U /* 1 = enable unicast hash */
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#define ETH_CFG_MTI 0x0040U /* 1 = enable multicast hash */
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#define ETH_CFG_NBC 0x0020U /* 1 = ignore received broadcasts */
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#define ETH_CFG_CAF 0x0010U /* 1 = receive all valid frames */
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#define ETH_CFG_BR 0x0004U
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#define ETH_CFG_FD 0x0002U /* 1 = force full duplex */
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#define ETH_CFG_SPD 0x0001U /* 1 = 100 Mbps */
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#define GEM_CFG_GEN __BIT(10)
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#define GEM_CFG_CLK __BITS(20, 18)
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#define GEM_CFG_CLK_8 __SHIFTIN(0, GEM_CFG_CLK)
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#define GEM_CFG_CLK_16 __SHIFTIN(1, GEM_CFG_CLK)
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#define GEM_CFG_CLK_32 __SHIFTIN(2, GEM_CFG_CLK)
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#define GEM_CFG_CLK_48 __SHIFTIN(3, GEM_CFG_CLK)
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#define GEM_CFG_CLK_64 __SHIFTIN(4, GEM_CFG_CLK)
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#define GEM_CFG_CLK_96 __SHIFTIN(5, GEM_CFG_CLK)
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#define GEM_CFG_DBW __BITS(22, 21)
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#define GEM_CFG_RX_CHKSUM_OFFLD_EN __BIT(24)
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/* Status Register bits: */
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#define ETH_SR_IDLE 0x0004U /* 1 = PHY logic is running */
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#define ETH_SR_MDIO 0x0002U /* 1 = MDIO pin set */
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#define ETH_SR_LINK 0x0001U
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/* Transmit Control Register bits: */
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#define ETH_TCR_NCRC 0x8000U /* 1 = don't append CRC */
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#define ETH_TCR_LEN 0x07FFU /* transmit frame length */
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/* Transmit Status Register bits: */
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#define ETH_TSR_UND 0x40U /* 1 = transmit underrun detected */
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#define ETH_TSR_COMP 0x20U /* 1 = transmit complete */
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#define ETH_TSR_BNQ 0x10U /* 1 = transmit buffer not queued (at91rm9200 only) */
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#define ETH_TSR_IDLE 0x08U /* 1 = transmitter idle */
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#define ETH_TSR_RLE 0x04U /* 1 = retry limit exceeded */
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#define ETH_TSR_COL 0x02U /* 1 = collision occurred */
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#define ETH_TSR_OVR 0x01U /* 1 = transmit buffer overrun */
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#define GEM_TSR_TXGO __BIT(3)
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/* Receive Status Register bits: */
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#define ETH_RSR_OVR 0x04U /* 1 = RX overrun */
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#define ETH_RSR_REC 0x02U /* 1 = frame received */
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#define ETH_RSR_BNA 0x01U /* 1 = buffer not available */
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/* Interrupt bits: */
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#define ETH_ISR_ABT 0x0800U /* 1 = abort during DMA transfer */
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#define ETH_ISR_ROVR 0x0400U /* 1 = RX overrun */
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#define ETH_ISR_LINK 0x0200U /* 1 = link pin changed */
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#define ETH_ISR_TIDLE 0x0100U /* 1 = transmitter idle */
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#define ETH_ISR_TCOM 0x0080U /* 1 = transmit complete */
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#define ETH_ISR_TBRE 0x0040U /* 1 = transmit buffer register empty */
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#define ETH_ISR_RTRY 0x0020U /* 1 = retry limit exceeded */
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#define ETH_ISR_TUND 0x0010U /* 1 = transmit buffer underrun */
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#define ETH_ISR_TOVR 0x0008U /* 1 = transmit buffer overrun */
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#define ETH_ISR_RBNA 0x0004U /* 1 = receive buffer not available */
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#define ETH_ISR_RCOM 0x0002U /* 1 = receive complete */
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#define ETH_ISR_DONE 0x0001U /* 1 = management done */
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/* PHY Maintenance Register bits: */
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#define ETH_MAN_LOW 0x80000000U /* must not be set */
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#define ETH_MAN_HIGH 0x40000000U /* must be set */
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#define ETH_MAN_RW 0x30000000U
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#define ETH_MAN_RW_RD 0x20000000U
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#define ETH_MAN_RW_WR 0x10000000U
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#define ETH_MAN_PHYA 0x0F800000U /* PHY address (normally 0) */
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#define ETH_MAN_PHYA_SHIFT 23U
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#define ETH_MAN_REGA 0x007C0000U
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#define ETH_MAN_REGA_SHIFT 18U
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#define ETH_MAN_CODE 0x00030000U /* must be 10 */
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#define ETH_MAN_CODE_IEEE802_3 \
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0x00020000U
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#define ETH_MAN_DATA 0x0000FFFFU /* data to be written to the PHY */
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#define ETH_MAN_VAL (ETH_MAN_HIGH|ETH_MAN_CODE_IEEE802_3)
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/* received buffer descriptor: */
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#define ETH_DSC_ADDR 0x00U
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#define ETH_DSC_FLAGS 0x00U
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#define ETH_DSC_INFO 0x04U
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#define ETH_DSC_SIZE 0x08U
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typedef struct eth_dsc {
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volatile uint32_t Addr;
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volatile uint32_t Info;
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} __attribute__ ((aligned(4))) eth_dsc_t;
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/* flags: */
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#define ETH_RDSC_F_WRAP 0x00000002U
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#define ETH_RDSC_F_USED 0x00000001U
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/* frame info bits: */
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#define ETH_RDSC_I_BCAST __BIT(31)
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#define ETH_RDSC_I_MULTICAST __BIT(30)
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#define ETH_RDSC_I_UNICAST __BIT(29)
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#define ETH_RDSC_I_VLAN 0x10000000U
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#define ETH_RDSC_I_UNKNOWN_SRC 0x08000000U
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#define ETH_RDSC_I_MATCH1 0x04000000U
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#define ETH_RDSC_I_MATCH2 0x02000000U
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#define ETH_RDSC_I_MATCH3 0x01000000U
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#define ETH_RDSC_I_MATCH4 0x00800000U
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#define ETH_RDSC_I_CHKSUM __BITS(23, 22)
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#define ETH_RDSC_I_CHKSUM_NONE __SHIFTIN(0, ETH_RDSC_I_CHKSUM)
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#define ETH_RDSC_I_CHKSUM_IP __SHIFTIN(1, ETH_RDSC_I_CHKSUM)
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#define ETH_RDSC_I_CHKSUM_TCP __SHIFTIN(2, ETH_RDSC_I_CHKSUM)
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#define ETH_RDSC_I_CHKSUM_UDP __SHIFTIN(3, ETH_RDSC_I_CHKSUM)
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#define ETH_RDSC_I_LEN __BITS(13, 0)
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#define ETH_TDSC_I_USED __BIT(31) /* done transmitting */
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#define ETH_TDSC_I_WRAP __BIT(30) /* end of descr ring */
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#define ETH_TDSC_I_RETRY_ERR __BIT(29)
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#define ETH_TDSC_I_AHB_ERR __BIT(27)
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#define ETH_TDSC_I_LATE_COLL __BIT(26)
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#define ETH_TDSC_I_CHKSUM __BITS(22, 20)
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#define ETH_TDSC_I_CHKSUM_GEN_STAT_NO_ERR __SHIFTIN(0, ETH_TDSC_I_CHKSUM)
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#define ETH_TDSC_I_CHKSUM_GEN_STAT_VLAN_HDR_ERR __SHIFTIN(1, ETH_TDSC_I_CHKSUM)
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#define ETH_TDSC_I_CHKSUM_GEN_STAT_SNAP_HDR_ERR __SHIFTIN(2, ETH_TDSC_I_CHKSUM)
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#define ETH_TDSC_I_CHKSUM_GEN_STAT_IP_HDR_ERR __SHIFTIN(3, ETH_TDSC_I_CHKSUM)
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#define ETH_TDSC_I_CHKSUM_GEN_STAT_UNKNOWN_TYPE __SHIFTIN(4, ETH_TDSC_I_CHKSUM)
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#define ETH_TDSC_I_CHKSUM_GEN_STAT_UNSUPP_FRAG __SHIFTIN(5, ETH_TDSC_I_CHKSUM)
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#define ETH_TDSC_I_CHKSUM_GEN_STAT_NOT_TCPUDP __SHIFTIN(6, ETH_TDSC_I_CHKSUM)
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#define ETH_TDSC_I_CHKSUM_GEN_STAT_SHORT_PKT __SHIFTIN(7, ETH_TDSC_I_CHKSUM)
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#define ETH_TDSC_I_NO_CRC_APPENDED __BIT(16)
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#define ETH_TDSC_I_LAST_BUF __BIT(15) /* last buf in frame */
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#define ETH_TDSC_I_LEN __BITS(13, 0)
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#endif /* !_IF_CEMACREG_H_ */
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