154 lines
6.1 KiB
C
154 lines
6.1 KiB
C
/* $NetBSD: vrpmureg.h,v 1.2 1999/12/08 01:51:56 sato Exp $ */
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/*-
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* Copyright (c) 1999 SATO Kazumi. All rights reserved.
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* Copyright (c) 1999 PocketBSD Project. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the PocketBSD project
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* and its contributors.
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* 4. Neither the name of the project nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* PMU (Power Management Unit) Registers definitions.
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* start 0xB0000A0
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*/
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#define PMUINT_REG_W 0x000 /* PMU interrupt/Status Register */
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#define PMUINT_GPIO3 (1<<15) /* GPIO3 */
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#define PMUINT_GPIO2 (1<<14) /* GPIO2 */
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#define PMUINT_GPIO1 (1<<13) /* GPIO1 */
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#define PMUINT_GPIO0 (1<<12) /* GPIO0 */
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#define PMUINT_DCDST (1<<10) /* DCD# */
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#define PMUINT_RTC (1<<9) /* RTC Alarm */
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#define PMUINT_BATT (1<<8) /* BATTERY LOW */
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#define PMUINT_TIMOUTRST (1<<5) /* HAL Timer Reset */
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#define PMUINT_RTCRST (1<<4) /* RTC Reset */
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#define PMUINT_RSTSWRST (1<<3) /* Reset SW */
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#define PMUINT_DMSWRST (1<<2) /* Deadman's SW */
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#define PMUINT_BATTINTR (1<<1) /* Low batt during normal operation */
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#define PMUINT_POWERSW (1) /* Power Switch */
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#define PMUINT_ALL (PMUINT_GPIO3|PMUINT_GPIO2|\
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PMUINT_GPIO1|PMUINT_GPIO0|\
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PMUINT_DCDST|PMUINT_RTC|\
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PMUINT_BATT|PMUINT_TIMOUTRST|\
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PMUINT_RTCRST|PMUINT_RSTSWRST|\
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PMUINT_DMSWRST|PMUINT_BATTINTR|\
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PMUINT_POWERSW)
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#define PMUCNT_REG_W 0x002 /* PMU Control Register */
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#define PMUCNT_GPIO3MASK (1<<15) /* GPIO3 MASK */
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#define PMUCNT_GPIO3EN (1<<15) /* GPIO3 Enable */
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#define PMUCNT_GPIO3DS (0<<15) /* GPIO3 Disable */
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#define PMUCNT_GPIO2MASK (1<<14) /* GPIO2 MASK */
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#define PMUCNT_GPIO2EN (1<<14) /* GPIO2 Enable */
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#define PMUCNT_GPIO2DS (0<<14) /* GPIO2 Disable */
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#define PMUCNT_GPIO1MASK (1<<13) /* GPIO1 MASK */
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#define PMUCNT_GPIO1EN (1<<13) /* GPIO1 Enable */
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#define PMUCNT_GPIO1DS (0<<13) /* GPIO1 Disable */
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#define PMUCNT_GPIO0MASK (1<<12) /* GPIO0 MASK */
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#define PMUCNT_GPIO0EN (1<<12) /* GPIO0 Enable */
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#define PMUCNT_GPIO0DS (0<<12) /* GPIO0 Disable */
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#define PMUCNT_GPIO3TRIG (1<<11) /* GPIO3 TRIG */
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#define PMUCNT_GPIO3D (1<<11) /* GPIO3 Fall */
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#define PMUCNT_GPIO3U (0<<11) /* GPIO3 Raise */
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#define PMUCNT_GPIO2TRIG (1<<10) /* GPIO2 TRIG */
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#define PMUCNT_GPIO2D (1<<10) /* GPIO2 Fall */
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#define PMUCNT_GPIO2U (0<<10) /* GPIO2 Raise */
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#define PMUCNT_GPIO1TRIG (1<<9) /* GPIO1 TRIG */
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#define PMUCNT_GPIO1D (1<<9) /* GPIO1 Fall */
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#define PMUCNT_GPIO1U (0<<9) /* GPIO1 Raise */
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#define PMUCNT_GPIO0TRIG (1<<8) /* GPIO0 TRIG */
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#define PMUCNT_GPIO0D (1<<8) /* GPIO0 Fall */
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#define PMUCNT_GPIO0U (0<<8) /* GPIO0 Raise */
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#define PMUCNT_HALTIMERRST (1<<2) /* HAL Timer Reset */
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#define PMUCNT_ONE (1<<1) /* ALWAYS write 1 */
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#define PMUINT2_REG_W 0x004 /* PMU interrupt/Status Register 2 */
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#define PMUINT_GPIO12 (1<<15) /* GPIO12 */
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#define PMUINT_GPIO11 (1<<14) /* GPIO11 */
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#define PMUINT_GPIO10 (1<<13) /* GPIO10 */
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#define PMUINT_GPIO9 (1<<12) /* GPIO9 */
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#define PMUINT2_ALL (PMUINT_GPIO12|PMUINT_GPIO11|\
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PMUINT_GPIO10|PMUINT_GPIO9)
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#define PMUCNT2_REG_W 0x006 /* PMU Control Register 2 */
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#define PMUCNT_GPIO12MASK (1<<15) /* GPIO12 MASK */
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#define PMUCNT_GPIO12EN (1<<15) /* GPIO12 Enable */
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#define PMUCNT_GPIO12DS (0<<15) /* GPIO12 Disable */
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#define PMUCNT_GPIO11MASK (1<<14) /* GPIO11 MASK */
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#define PMUCNT_GPIO11EN (1<<14) /* GPIO11 Enable */
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#define PMUCNT_GPIO11DS (0<<14) /* GPIO11 Disable */
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#define PMUCNT_GPIO10MASK (1<<13) /* GPIO10 MASK */
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#define PMUCNT_GPIO10EN (1<<13) /* GPIO10 Enable */
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#define PMUCNT_GPIO10DS (0<<13) /* GPIO10 Disable */
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#define PMUCNT_GPIO9MASK (1<<12) /* GPIO9 MASK */
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#define PMUCNT_GPIO9EN (1<<12) /* GPIO9 Enable */
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#define PMUCNT_GPIO9DS (0<<12) /* GPIO9 Disable */
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#define PMUCNT_GPIO12TRIG (1<<11) /* GPIO12 TRIG */
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#define PMUCNT_GPIO12D (1<<11) /* GPIO12 Fail */
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#define PMUCNT_GPIO12U (0<<11) /* GPIO12 Raise */
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#define PMUCNT_GPIO11TRIG (1<<10) /* GPIO11 TRIG */
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#define PMUCNT_GPIO11D (1<<10) /* GPIO11 Fail */
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#define PMUCNT_GPIO11U (0<<10) /* GPIO11 Raise */
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#define PMUCNT_GPIO10TRIG (1<<9) /* GPIO10 TRIG */
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#define PMUCNT_GPIO10D (1<<9) /* GPIO10 Fail */
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#define PMUCNT_GPIO10U (0<<9) /* GPIO10 Raise */
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#define PMUCNT_GPIO9TRIG (1<<8) /* GPIO9 TRIG */
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#define PMUCNT_GPIO9D (1<<8) /* GPIO9 Fail */
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#define PMUCNT_GPIO9U (0<<8) /* GPIO9 Raise */
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#define PMUWAIT_REG_W 0x008 /* PMU Wait Control Register */
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#define PMUWAIT_DEFAULT 0x2c00 /* 343.75ms */
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#define PMUDIV_REG_W 0x00C /* PMU Div Mode Register (vr4121) */
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/* END vrpmureg.h */
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