262 lines
6.7 KiB
C
262 lines
6.7 KiB
C
/* $NetBSD: pci_a12.c,v 1.1 1998/01/29 21:42:53 ross Exp $ */
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/* [Notice revision 2.0]
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* Copyright (c) 1997 Avalon Computer Systems, Inc.
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* All rights reserved.
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*
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* Author: Ross Harvey
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright and
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* author notice, this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of Avalon Computer Systems, Inc. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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* 4. This copyright will be assigned to The NetBSD Foundation on
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* 1/1/2000 unless these terms (including possibly the assignment
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* date) are updated in writing by Avalon prior to the latest specified
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* assignment date.
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*
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* THIS SOFTWARE IS PROVIDED BY AVALON COMPUTER SYSTEMS, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "opt_avalon_a12.h" /* Config options headers */
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: pci_a12.c,v 1.1 1998/01/29 21:42:53 ross Exp $");
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/time.h>
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#include <sys/systm.h>
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#include <sys/errno.h>
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#include <sys/malloc.h>
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#include <sys/device.h>
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#include <sys/syslog.h>
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#include <vm/vm.h>
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#include <machine/autoconf.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <alpha/pci/a12creg.h>
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#include <alpha/pci/a12cvar.h>
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#include <alpha/pci/pci_a12.h>
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#ifndef EVCNT_COUNTERS
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#include <machine/intrcnt.h>
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#endif
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int avalon_a12_intr_map __P((void *, pcitag_t, int, int,
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pci_intr_handle_t *));
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const char *avalon_a12_intr_string __P((void *, pci_intr_handle_t));
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void *avalon_a12_intr_establish __P((void *, pci_intr_handle_t,
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int, int (*func)(void *), void *));
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void avalon_a12_intr_disestablish __P((void *, void *));
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static void clear_gsr_interrupt __P((long));
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static void a12_pci_icall __P((int));
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static void pci_serr __P((int));
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static void a12_xbar_flag __P((int));
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static void a12_interval __P((int));
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static void a12_check_cdr __P((int));
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#ifdef EVCNT_COUNTERS
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struct evcnt a12_intr_evcnt;
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#endif
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static int (*a12_established_device) __P((void *));
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static void *ih_arg;
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void a12_iointr __P((void *framep, unsigned long vec));
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void
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pci_a12_pickintr(ccp)
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struct a12c_config *ccp;
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{
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pci_chipset_tag_t pc = &ccp->ac_pc;
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pc->pc_intr_v = ccp;
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pc->pc_intr_map = avalon_a12_intr_map;
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pc->pc_intr_string = avalon_a12_intr_string;
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pc->pc_intr_establish = avalon_a12_intr_establish;
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pc->pc_intr_disestablish = avalon_a12_intr_disestablish;
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set_iointr(a12_iointr);
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}
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int
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avalon_a12_intr_map(ccv, bustag, buspin, line, ihp)
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void *ccv;
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pcitag_t bustag;
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int buspin, line;
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pci_intr_handle_t *ihp;
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{
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/* only one PCI slot (per CPU, that is, but there are 12 CPU's!) */
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*ihp = 0;
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return 0;
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}
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const char *
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avalon_a12_intr_string(ccv, ih)
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void *ccv;
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pci_intr_handle_t ih;
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{
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return "a12 pci irq"; /* see "only one" note above */
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}
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void *
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avalon_a12_intr_establish(ccv, ih, level, func, arg)
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void *ccv, *arg;
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pci_intr_handle_t ih;
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int level;
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int (*func) __P((void *));
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{
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if(a12_established_device)
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panic("avalon_a12_intr_establish");
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a12_established_device = func;
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ih_arg = arg;
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REGVAL(A12_OMR) |= 1<<7;
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return (void *)func;
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}
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void
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avalon_a12_intr_disestablish(ccv, cookie)
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void *ccv, *cookie;
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{
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if(cookie==a12_established_device)
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a12_established_device = 0;
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else What();
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}
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long a12_nothing;
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static void
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clear_gsr_interrupt(write_1_to_clear)
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long write_1_to_clear;
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{
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REGVAL(A12_GSR) = write_1_to_clear;
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alpha_mb();
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a12_nothing = REGVAL(A12_GSR);
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}
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static void a12_pci_icall(i)
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{
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if(a12_established_device) {
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(*a12_established_device)(ih_arg);
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return;
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}
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printf("PCI irq rcvd, but no handler established.\n");
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}
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static void pci_serr(i) { panic("pci_serr"); }
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static void a12_xbar_flag(i) { panic("a12_xbar_flag"); }
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static void a12_interval(i) { panic("a12_interval"); }
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static void a12_check_cdr(i)
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{
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}
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static struct gintcall {
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char flag;
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char needsclear;
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char intr_index; /* XXX implicit crossref */
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void (*f)(int);
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} gintcall[] = {
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{ 6, 0, 2, a12_pci_icall },
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{ 7, 1, 3, pci_serr },
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{ 8, 1, 4, a12_xbar_flag },
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{ 9, 1, 5, a12_xbar_flag },
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/* skip 10, gsr.TEI */
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{ 11, 1, 6, a12_interval },
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{ 12, 1, 7, a12_xbar_flag },
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{ 13, 1, 8, a12_xbar_flag },
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{ 14, 1, 9, a12_check_cdr },
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{ 0 }
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};
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static void a12_GInt(void);
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static void a12_GInt(void)
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{
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struct gintcall *gic;
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long gsrvalue = REGVAL(A12_GSR) & 0x7fc0;
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for(gic=gintcall; gic->f; ++gic) {
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if(gsrvalue & 1L<<gic->flag) {
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#ifndef EVCNT_COUNTERS
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if (gic->intr_index >= INTRCNT_A12_IRQ_LEN)
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panic("A12 INTRCNT");
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intrcnt[INTRCNT_A12_IRQ + gic->intr_index];
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#endif
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if(gic->needsclear)
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clear_gsr_interrupt(1L<<gic->flag);
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(*gic->f)(gic->flag);
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alpha_wmb();
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}
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}
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}
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static void a12_xbar_omchint(void);
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static void a12_xbar_omchint() { panic("a12_xbar_omchint"); };
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static void a12_xbar_imchint(void);
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static void a12_xbar_imchint() { panic("a12_xbar_imchint"); };
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void
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a12_iointr(framep, vec)
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void *framep;
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unsigned long vec;
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{
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unsigned irq = (vec-0x900) >> 4;
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/*
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* Xbar device is in the A12 CPU core logic, so its interrupts
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* might as well be hardwired.
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*/
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#ifdef EVCNT_COUNTERS
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++a12_intr_evcnt.ev_count;
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#else
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/* XXX implicit knowledge of intrcnt[] */
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if(irq < 2)
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++intrcnt[INTRCNT_A12_IRQ + irq];
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#if 2 >= INTRCNT_A12_IRQ_LEN
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#error INTRCNT_A12_IRQ_LEN inconsistent with respect to intrcnt[] use
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#endif
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#endif
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switch(irq) {
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case 0:
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a12_xbar_omchint();
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return;
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case 1:
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a12_xbar_imchint();
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return;
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case 2:
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a12_GInt();
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return;
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default:
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panic("a12_iointr");
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}
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}
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