c8c49f7222
- vrc4172 gpio/ucy/pcs/pmu/pwm register definitions. - vrc4172 pwm driver (not yet completely)
71 lines
2.4 KiB
C
71 lines
2.4 KiB
C
/* $NetBSD: vrc4172pcsreg.h,v 1.1 2000/11/11 04:42:09 sato Exp $ */
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/*
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* Copyright (c) 2000 SATO Kazumi. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Vrc4172 PCS (Programable Chip Select) Unit Registers.
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*/
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#define VRC2_EXCSREG_MAX 0x30
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#define VRC2_EXCS0SELL 0x00
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#define VRC2_EXCS0SELH 0x02
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#define VRC2_EXCS0MSKL 0x04
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#define VRC2_EXCS0MSKH 0x06
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#define VRC2_EXCS1SELL 0x08
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#define VRC2_EXCS1SELH 0x0a
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#define VRC2_EXCS1MSKL 0x0c
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#define VRC2_EXCS1MSKH 0x0e
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#define VRC2_EXCS2SELL 0x10
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#define VRC2_EXCS2SELH 0x12
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#define VRC2_EXCS2MSKL 0x14
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#define VRC2_EXCS2MSKH 0x16
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#define VRC2_EXCS3SELL 0x18
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#define VRC2_EXCS3SELH 0x1a
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#define VRC2_EXCS3MSKL 0x1c
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#define VRC2_EXCS3MSKH 0x1e
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#define VRC2_EXCS4SELL 0x20
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#define VRC2_EXCS4SELH 0x22
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#define VRC2_EXCS4MSKL 0x24
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#define VRC2_EXCS4MSKH 0x26
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#define VRC2_EXCS5SELL 0x28
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#define VRC2_EXCS5SELH 0x2a
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#define VRC2_EXCS5MSKL 0x2c
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#define VRC2_EXCS5MSKH 0x2e
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/* for EXCSnSELL */
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#define VRC2_EXCSSELLMASK 0xfffe
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/* for EXCSnSELH */
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#define VRC2_EXCSSELHMASK 0x01ff
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/* for EXCSnMSKL */
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#define VRC2_EXCSENMASK 0x1
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#define VRC2_EXCSEN 0x1
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#define VRC2_EXCSDIS 0x00
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#define VRC2_EXCSMSKLMASK 0xfffe
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/* for EXCSnMSKH */
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#define VRC2_EXCSMSKHMASK 0x01ff
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/* end */
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