417 lines
11 KiB
C
417 lines
11 KiB
C
/* $NetBSD: vr4181aiu.c,v 1.1 2003/05/01 07:02:04 igy Exp $ */
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/*
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* Copyright (c) 2002 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Naoto Shimazaki of YOKOGAWA Electric Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/conf.h>
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#include <sys/device.h>
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#include <sys/errno.h>
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#include <sys/malloc.h>
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#include <sys/proc.h>
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#include <sys/systm.h>
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#include <mips/cpuregs.h>
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#include <machine/bus.h>
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#include <hpcmips/vr/vripif.h>
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#include <hpcmips/vr/vr4181aiureg.h>
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#include <hpcmips/vr/vr4181dcureg.h>
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#define INBUFLEN 1024 /* length in u_int16_t */
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#define INPUTLEN 1000
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#define SAMPLEFREQ 1000
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#define PICKUPFREQ 100
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#define PICKUPCOUNT (SAMPLEFREQ / PICKUPFREQ)
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#define ST_BUSY 0x01
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#define ST_OVERRUN 0x02
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#define INBUF_MASK 0x3ff /* 2Kbyte */
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#define INBUF_RAW_SIZE (INBUFLEN * 4 + (INBUF_MASK + 1))
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#ifdef VR4181AIU_DEBUG
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int vr4181aiu_debug = 0;
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#define DPRINTF(x) if (vr4181aiu_debug) printf x
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#else
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#define DPRINTF(x)
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#endif
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struct vr4181aiu_softc {
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struct device sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_dcu1_ioh;
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bus_space_handle_t sc_dcu2_ioh;
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bus_space_handle_t sc_aiu_ioh;
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u_int16_t *sc_inbuf_head;
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u_int16_t *sc_inbuf_tail;
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u_int16_t *sc_inbuf_which;
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u_int16_t *sc_inbuf1;
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u_int16_t *sc_inbuf2;
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u_int16_t *sc_inbuf_raw;
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int sc_status;
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};
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static int vr4181aiu_match(struct device *, struct cfdata *, void *);
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static void vr4181aiu_attach(struct device *, struct device *, void *);
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static int vr4181aiu_intr(void *);
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extern struct cfdriver vr4181aiu_cd;
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CFATTACH_DECL(vr4181aiu, sizeof(struct vr4181aiu_softc),
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vr4181aiu_match, vr4181aiu_attach, NULL, NULL);
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dev_type_open(vr4181aiuopen);
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dev_type_close(vr4181aiuclose);
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dev_type_read(vr4181aiuread);
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dev_type_write(vr4181aiuwrite);
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const struct cdevsw vr4181aiu_cdevsw = {
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vr4181aiuopen, vr4181aiuclose, vr4181aiuread, vr4181aiuwrite, noioctl,
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nostop, notty, nopoll, nommap, nokqfilter,
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};
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static int
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vr4181aiu_match(struct device *parent, struct cfdata *cf, void *aux)
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{
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return 1;
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}
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static void
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vr4181aiu_init_inbuf(struct vr4181aiu_softc *sc)
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{
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/*
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* XXXXXXXXXXXXXXXXX
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*
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* this is just a quick and dirty hack to locate the buffer
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* in KSEG0 space. the only reason is that i want the physical
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* address of the buffer.
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*
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* bus_dma framework should be used.
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*/
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static char inbufbase[INBUF_RAW_SIZE];
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sc->sc_inbuf_raw = (u_int16_t *) inbufbase;
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sc->sc_inbuf1 = (u_int16_t *) ((((u_int32_t) sc->sc_inbuf_raw)
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+ INBUF_MASK)
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& ~INBUF_MASK);
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sc->sc_inbuf2 = sc->sc_inbuf1 + INBUFLEN;
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}
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static void
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vr4181aiu_disable(struct vr4181aiu_softc *sc)
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{
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/* irq clear */
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bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh,
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DCU_DMAITRQ_REG_W, DCU_MICEOP);
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bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh,
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VR4181AIU_INT_REG_W,
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VR4181AIU_MIDLEINTR
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| VR4181AIU_MSTINTR
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| VR4181AIU_SIDLEINTR);
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/* disable microphone */
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bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh,
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VR4181AIU_SEQ_REG_W, 0);
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/* disable ADC */
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bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh,
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VR4181AIU_MCNT_REG_W, 0);
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/* disable DMA */
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bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh,
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DCU_AIUDMAMSK_REG_W, 0);
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bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh,
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DCU_DMAITMK_REG_W, 0);
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sc->sc_status = 0;
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}
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static void
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vr4181aiu_attach(struct device *parent, struct device *self, void *aux)
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{
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struct vrip_attach_args *va = aux;
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struct vr4181aiu_softc *sc = (void *) self;
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vr4181aiu_init_inbuf(sc);
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memset(sc->sc_inbuf1, 0x55, INBUFLEN * 2);
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memset(sc->sc_inbuf2, 0xaa, INBUFLEN * 2);
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sc->sc_status = 0;
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sc->sc_iot = va->va_iot;
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if (bus_space_map(sc->sc_iot,
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VR4181AIU_DCU1_BASE, VR4181AIU_DCU1_SIZE,
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0, &sc->sc_dcu1_ioh))
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goto out_dcu1;
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if (bus_space_map(sc->sc_iot,
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VR4181AIU_DCU2_BASE, VR4181AIU_DCU2_SIZE,
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0, &sc->sc_dcu2_ioh))
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goto out_dcu2;
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if (bus_space_map(sc->sc_iot,
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VR4181AIU_AIU_BASE, VR4181AIU_AIU_SIZE,
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0, &sc->sc_aiu_ioh))
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goto out_aiu;
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/*
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* reset AIU
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*/
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bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh,
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VR4181AIU_SEQ_REG_W, VR4181AIU_AIURST);
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bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh,
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VR4181AIU_SEQ_REG_W, 0);
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/*
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* set sample rate (1kHz fixed)
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* XXXX
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* assume to PCLK is 32.768MHz
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*/
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bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh,
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VR4181AIU_MCNVC_END,
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32768000 / SAMPLEFREQ);
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/*
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* XXXX
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* assume to PCLK is 32.768MHz
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* DAVREF_SETUP = 5usec * PCLK = 163.84
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*/
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bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh,
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VR4181AIU_DAVREF_SETUP_REG_W, 164);
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vr4181aiu_disable(sc);
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if (vrip_intr_establish(va->va_vc, va->va_unit, 0,
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IPL_BIO, vr4181aiu_intr, sc) == NULL) {
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printf("%s: can't establish interrupt\n",
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sc->sc_dev.dv_xname);
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return;
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}
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printf("\n");
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return;
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out_aiu:
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bus_space_unmap(sc->sc_iot, sc->sc_dcu2_ioh, VR4181AIU_DCU2_SIZE);
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out_dcu2:
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bus_space_unmap(sc->sc_iot, sc->sc_dcu1_ioh, VR4181AIU_DCU1_SIZE);
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out_dcu1:
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printf(": can't map i/o space\n");
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}
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int
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vr4181aiuopen(dev_t dev, int flag, int mode, struct proc *p)
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{
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struct vr4181aiu_softc *sc;
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if ((sc = device_lookup(&vr4181aiu_cd, minor(dev))) == NULL)
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return ENXIO;
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if (sc->sc_status & ST_BUSY)
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return EBUSY;
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sc->sc_inbuf_head = sc->sc_inbuf_tail
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= sc->sc_inbuf_which = sc->sc_inbuf1;
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sc->sc_status &= ~ST_OVERRUN;
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/* setup DMA */
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/* reset */
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bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh,
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DCU_DMARST_REG_W, 0);
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bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh,
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DCU_DMARST_REG_W, DCU_DMARST);
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/* dest1 <- sc_inbuf1 */
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bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh,
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DCU_MICDEST1REG1_W,
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MIPS_KSEG0_TO_PHYS(sc->sc_inbuf1) & 0xffff);
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bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh,
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DCU_MICDEST1REG2_W,
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MIPS_KSEG0_TO_PHYS(sc->sc_inbuf1) >> 16);
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/* dest2 <- sc_inbuf2 */
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bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh,
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DCU_MICDEST2REG1_W,
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MIPS_KSEG0_TO_PHYS(sc->sc_inbuf2) & 0xffff);
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bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh,
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DCU_MICDEST2REG2_W,
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MIPS_KSEG0_TO_PHYS(sc->sc_inbuf2) >> 16);
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/* record length <- INPUTLEN */
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bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh,
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DCU_MICRCLEN_REG_W, INPUTLEN);
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/* config <- auto load */
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bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh,
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DCU_MICDMACFG_REG_W, DCU_MICLOAD);
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/* irq <- irq clear */
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bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh,
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DCU_DMAITRQ_REG_W, DCU_MICEOP);
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/* control <- INC */
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bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh,
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DCU_DMACTL_REG_W, DCU_MICCNT_INC);
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/* irq mask <- microphone end of process */
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bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh,
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DCU_DMAITMK_REG_W, DCU_MICEOP_ENABLE);
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/* enable DMA */
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bus_space_write_2(sc->sc_iot, sc->sc_dcu1_ioh,
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DCU_AIUDMAMSK_REG_W, DCU_ENABLE_MIC);
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/* enable ADC */
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bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh,
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VR4181AIU_MCNT_REG_W, VR4181AIU_ADENAIU);
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/* enable microphone */
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bus_space_write_2(sc->sc_iot, sc->sc_aiu_ioh,
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VR4181AIU_SEQ_REG_W, VR4181AIU_AIUMEN);
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sc->sc_status |= ST_BUSY;
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return 0;
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}
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int
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vr4181aiuclose(dev_t dev, int flag, int mode, struct proc *p)
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{
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vr4181aiu_disable(device_lookup(&vr4181aiu_cd, minor(dev)));
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return 0;
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}
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int
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vr4181aiuread(dev_t dev, struct uio *uio, int flag)
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{
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struct vr4181aiu_softc *sc;
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int s;
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u_int16_t *fence;
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int avail;
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int count;
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u_int8_t tmp[INPUTLEN / PICKUPCOUNT];
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u_int16_t *src;
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u_int8_t *dst;
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sc = device_lookup(&vr4181aiu_cd, minor(dev));
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src = sc->sc_inbuf_tail;
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s = splbio();
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if (src == sc->sc_inbuf_head) {
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/* wait for DMA to complete writing */
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tsleep(sc, PRIBIO, "aiu read", 0);
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/* now sc_inbuf_head points alternate buffer */
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}
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splx(s);
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fence = sc->sc_inbuf_which == sc->sc_inbuf1
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? &sc->sc_inbuf1[INPUTLEN]
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: &sc->sc_inbuf2[INPUTLEN];
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avail = (fence - src) / PICKUPCOUNT;
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count = min(avail, uio->uio_resid);
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dst = tmp;
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while (count > 0) {
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*dst++ = (u_int8_t) (*src >> 2);
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src += PICKUPCOUNT;
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count--;
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}
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if (src < fence) {
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sc->sc_inbuf_tail = src;
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} else {
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/* alter the buffer */
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sc->sc_inbuf_tail
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= sc->sc_inbuf_which
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= sc->sc_inbuf_which == sc->sc_inbuf1
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? sc->sc_inbuf2 : sc->sc_inbuf1;
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}
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return uiomove(tmp, dst - tmp, uio);
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}
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int
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vr4181aiuwrite(dev_t dev, struct uio *uio, int flag)
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{
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return 0;
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}
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int
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vr4181aiupoll(dev_t dev, int events, struct proc *p)
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{
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return 0;
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}
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int
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vr4181aiuioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p)
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{
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return 0;
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}
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/*
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* interrupt handler
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*/
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static int
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vr4181aiu_intr(void *arg)
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{
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struct vr4181aiu_softc *sc = arg;
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if (!(sc->sc_status & ST_BUSY)) {
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printf("vr4181aiu_intr: stray interrupt\n");
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vr4181aiu_disable(sc);
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return 0;
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}
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/* irq clear */
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bus_space_write_2(sc->sc_iot, sc->sc_dcu2_ioh,
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DCU_DMAITRQ_REG_W, DCU_MICEOP);
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if (sc->sc_inbuf_head == sc->sc_inbuf1) {
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if (sc->sc_inbuf_tail != sc->sc_inbuf1)
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sc->sc_status |= ST_OVERRUN;
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sc->sc_inbuf_head = sc->sc_inbuf2;
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} else {
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if (sc->sc_inbuf_tail != sc->sc_inbuf2)
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sc->sc_status |= ST_OVERRUN;
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sc->sc_inbuf_head = sc->sc_inbuf1;
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}
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if (sc->sc_status & ST_OVERRUN) {
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printf("vr4181aiu_intr: overrun\n");
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}
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DPRINTF(("vr4181aiu_intr: sc_inbuf1 = %04x, sc_inbuf2 = %04x\n",
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sc->sc_inbuf1[0], sc->sc_inbuf2[0]));
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wakeup(sc);
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return 0;
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}
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