380 lines
10 KiB
C
380 lines
10 KiB
C
/* $NetBSD: asc_pmaz.c,v 1.2 2000/02/19 09:48:47 nisimura Exp $ */
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/*
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* Copyright (c) 2000 Tohru Nishimura. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Tohru Nishimura
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* for the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: asc_pmaz.c,v 1.2 2000/02/19 09:48:47 nisimura Exp $");
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/buf.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <dev/scsipi/scsi_message.h>
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#include <machine/bus.h>
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#include <dev/ic/ncr53c9xreg.h>
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#include <dev/ic/ncr53c9xvar.h>
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#include <dev/tc/tcvar.h>
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struct asc_softc {
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struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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void *sc_cookie; /* intr. handling cookie */
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bus_dma_tag_t sc_dmat;
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bus_dmamap_t sc_dmamap;
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int sc_active; /* DMA active ? */
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int sc_ispullup; /* DMA into main memory? */
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size_t sc_dmasize;
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caddr_t *sc_dmaaddr;
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size_t *sc_dmalen;
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/* XXX XXX XXX */
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caddr_t sc_base, sc_bounce, sc_target;
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};
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int asc_pmaz_match __P((struct device *, struct cfdata *, void *));
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void asc_pmaz_attach __P((struct device *, struct device *, void *));
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struct cfattach xasc_pmaz_ca = {
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sizeof(struct asc_softc), asc_pmaz_match, asc_pmaz_attach
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};
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struct scsipi_device asc_pmaz_dev = {
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NULL, /* Use default error handler */
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NULL, /* have a queue, served by this */
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NULL, /* have no async handler */
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NULL, /* Use default 'done' routine */
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};
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void asc_pmaz_reset __P((struct ncr53c9x_softc *));
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int asc_pmaz_intr __P((struct ncr53c9x_softc *));
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int asc_pmaz_setup __P((struct ncr53c9x_softc *, caddr_t *,
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size_t *, int, size_t *));
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void asc_pmaz_go __P((struct ncr53c9x_softc *));
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void asc_pmaz_stop __P((struct ncr53c9x_softc *));
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static u_char asc_read_reg __P((struct ncr53c9x_softc *, int));
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static void asc_write_reg __P((struct ncr53c9x_softc *, int, u_char));
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static int asc_dma_isintr __P((struct ncr53c9x_softc *));
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static int asc_dma_isactive __P((struct ncr53c9x_softc *));
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static void asc_clear_latched_intr __P((struct ncr53c9x_softc *));
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struct ncr53c9x_glue asc_pmaz_glue = {
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asc_read_reg,
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asc_write_reg,
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asc_dma_isintr,
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asc_pmaz_reset,
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asc_pmaz_intr,
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asc_pmaz_setup,
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asc_pmaz_go,
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asc_pmaz_stop,
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asc_dma_isactive,
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asc_clear_latched_intr,
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};
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/*
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* Parameters specific to PMAZ-A TC option card.
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*/
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#define PMAZ_OFFSET_53C94 0x0 /* from module base */
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#define PMAZ_OFFSET_DMAR 0x40000 /* DMA Address Register */
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#define PMAZ_OFFSET_RAM 0x80000 /* 128KB SRAM buffer */
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#define PMAZ_OFFSET_ROM 0xc0000 /* diagnostic ROM */
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#define PMAZ_RAM_SIZE 0x20000 /* 128k (32k*32) */
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#define PER_TGT_DMA_SIZE ((PMAZ_RAM_SIZE/7) & ~(sizeof(int)-1))
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#define PMAZ_DMAR_WRITE 0x80000000 /* DMA direction bit */
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#define PMAZ_DMAR_MASK 0x1ffff /* 17 bits, 128k */
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#define PMAZ_DMA_ADDR(x) ((unsigned)(x) & PMAZ_DMAR_MASK)
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int
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asc_pmaz_match(parent, cfdata, aux)
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struct device *parent;
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struct cfdata *cfdata;
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void *aux;
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{
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struct tc_attach_args *d = aux;
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if (strncmp("PMAZ-AA ", d->ta_modname, TC_ROM_LLEN))
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return (0);
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return (1);
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}
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void
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asc_pmaz_attach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct tc_attach_args *ta = aux;
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struct asc_softc *asc = (struct asc_softc *)self;
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struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x;
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#ifdef __pmax__
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extern int slot_in_progress; /* XXX TC slot being probed */
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slot_in_progress = ta->ta_slot; /* backdoor for dk_establish() */
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#endif
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/*
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* Set up glue for MI code early; we use some of it here.
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*/
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sc->sc_glue = &asc_pmaz_glue;
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asc->sc_bst = ta->ta_memt;
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asc->sc_dmat = ta->ta_dmat;
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if (bus_space_map(asc->sc_bst, ta->ta_addr,
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PMAZ_OFFSET_RAM + PMAZ_RAM_SIZE, 0, &asc->sc_bsh)) {
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printf("%s: unable to map device\n", sc->sc_dev.dv_xname);
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return;
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}
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asc->sc_cookie = ta->ta_cookie;
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asc->sc_base = (caddr_t)ta->ta_addr; /* XXX XXX XXX */
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tc_intr_establish(parent, asc->sc_cookie, IPL_BIO,
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(int (*)(void *))ncr53c9x_intr, sc);
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sc->sc_id = 7;
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sc->sc_freq = (ta->ta_busspeed) ? 25000000 : 12500000;
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/* gimme Mhz */
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sc->sc_freq /= 1000000;
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/*
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* XXX More of this should be in ncr53c9x_attach(), but
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* XXX should we really poke around the chip that much in
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* XXX the MI code? Think about this more...
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*/
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/*
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* Set up static configuration info.
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*/
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sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
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sc->sc_cfg2 = NCRCFG2_SCSI2;
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sc->sc_cfg3 = 0;
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sc->sc_rev = NCR_VARIANT_NCR53C94;
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/*
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* XXX minsync and maxxfer _should_ be set up in MI code,
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* XXX but it appears to have some dependency on what sort
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* XXX of DMA we're hooked up to, etc.
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*/
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/*
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* This is the value used to start sync negotiations
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* Note that the NCR register "SYNCTP" is programmed
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* in "clocks per byte", and has a minimum value of 4.
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* The SCSI period used in negotiation is one-fourth
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* of the time (in nanoseconds) needed to transfer one byte.
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* Since the chip's clock is given in MHz, we have the following
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* formula: 4 * period = (1000 / freq) * 4
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*/
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sc->sc_minsync = (1000 / sc->sc_freq) * 5 / 4;
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sc->sc_maxxfer = 64 * 1024;
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/* Do the common parts of attachment. */
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sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd;
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sc->sc_adapter.scsipi_minphys = minphys;
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ncr53c9x_attach(sc, &asc_pmaz_dev);
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}
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void
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asc_pmaz_reset(sc)
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struct ncr53c9x_softc *sc;
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{
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struct asc_softc *asc = (struct asc_softc *)sc;
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asc->sc_active = 0;
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}
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int
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asc_pmaz_intr(sc)
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struct ncr53c9x_softc *sc;
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{
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struct asc_softc *asc = (struct asc_softc *)sc;
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int trans, resid;
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resid = 0;
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if (!asc->sc_ispullup &&
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(resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
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NCR_DMA(("pmaz_intr: empty FIFO of %d ", resid));
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DELAY(1);
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}
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resid += NCR_READ_REG(sc, NCR_TCL);
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resid += NCR_READ_REG(sc, NCR_TCM) << 8;
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trans = asc->sc_dmasize - resid;
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if (asc->sc_ispullup)
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memcpy(asc->sc_target, asc->sc_bounce, trans);
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*asc->sc_dmalen -= trans;
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*asc->sc_dmaaddr += trans;
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asc->sc_active = 0;
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return (0);
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}
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int
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asc_pmaz_setup(sc, addr, len, datain, dmasize)
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struct ncr53c9x_softc *sc;
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caddr_t *addr;
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size_t *len;
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int datain;
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size_t *dmasize;
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{
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struct asc_softc *asc = (struct asc_softc *)sc;
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u_int32_t tc_dmar;
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size_t size;
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asc->sc_dmaaddr = addr;
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asc->sc_dmalen = len;
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asc->sc_ispullup = datain;
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NCR_DMA(("pmaz_setup: start %d@%p, %s\n",
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*asc->sc_dmalen, *asc->sc_dmaaddr, datain ? "IN" : "OUT"));
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size = *dmasize;
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if (size > PER_TGT_DMA_SIZE)
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size = PER_TGT_DMA_SIZE;
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*dmasize = asc->sc_dmasize = size;
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NCR_DMA(("pmaz_setup: dmasize = %d\n", asc->sc_dmasize));
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asc->sc_bounce = asc->sc_base + PMAZ_OFFSET_RAM;
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asc->sc_bounce += PER_TGT_DMA_SIZE *
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sc->sc_nexus->xs->sc_link->scsipi_scsi.target;
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asc->sc_target = *addr;
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if (!asc->sc_ispullup)
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memcpy(asc->sc_bounce, asc->sc_target, size);
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#if 1
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if (asc->sc_ispullup)
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tc_dmar = PMAZ_DMA_ADDR(asc->sc_bounce);
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else
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tc_dmar = PMAZ_DMAR_WRITE | PMAZ_DMA_ADDR(asc->sc_bounce);
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bus_space_write_4(asc->sc_bst, asc->sc_bsh, PMAZ_OFFSET_DMAR, tc_dmar);
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asc->sc_active = 1;
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#endif
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return (0);
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}
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void
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asc_pmaz_go(sc)
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struct ncr53c9x_softc *sc;
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{
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#if 0
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struct asc_softc *asc = (struct asc_softc *)sc;
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u_int32_t tc_dmar;
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if (asc->sc_ispullup)
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tc_dmar = PMAZ_DMA_ADDR(asc->sc_bounce);
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else
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tc_dmar = PMAZ_DMAR_WRITE | PMAZ_DMA_ADDR(asc->sc_bounce);
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bus_space_write_4(asc->sc_bst, asc->sc_bsh, PMAZ_OFFSET_DMAR, tc_dmar);
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asc->sc_active = 1;
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#endif
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}
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/* NEVER CALLED BY MI 53C9x ENGINE INDEED */
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void
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asc_pmaz_stop(sc)
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struct ncr53c9x_softc *sc;
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{
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#if 0
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struct asc_softc *asc = (struct asc_softc *)sc;
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if (asc->sc_ispullup)
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memcpy(asc->sc_target, asc->sc_bounce, asc->sc_dmasize);
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asc->sc_active = 0;
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#endif
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}
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/*
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* Glue functions.
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*/
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static u_char
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asc_read_reg(sc, reg)
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struct ncr53c9x_softc *sc;
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int reg;
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{
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struct asc_softc *asc = (struct asc_softc *)sc;
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u_char v;
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v = bus_space_read_4(asc->sc_bst, asc->sc_bsh,
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reg * sizeof(u_int32_t)) & 0xff;
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return (v);
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}
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static void
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asc_write_reg(sc, reg, val)
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struct ncr53c9x_softc *sc;
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int reg;
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u_char val;
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{
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struct asc_softc *asc = (struct asc_softc *)sc;
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bus_space_write_4(asc->sc_bst, asc->sc_bsh,
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reg * sizeof(u_int32_t), val);
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}
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static int
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asc_dma_isintr(sc)
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struct ncr53c9x_softc *sc;
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{
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return !!(NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT);
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}
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static int
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asc_dma_isactive(sc)
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struct ncr53c9x_softc *sc;
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{
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struct asc_softc *asc = (struct asc_softc *)sc;
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return (asc->sc_active);
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}
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static void
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asc_clear_latched_intr(sc)
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struct ncr53c9x_softc *sc;
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{
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}
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