95f41d24cc
(and only tested on) Intel Etherexpress PRO. Should work on any i82595 ISA board which uses an EEPROM for config information; NETBLKID not yet supported. TODO: change to BUS interface, add multicast support.
220 lines
5.8 KiB
C
220 lines
5.8 KiB
C
/* $NetBSD: i82595reg.h,v 1.1 1996/05/06 21:36:51 is Exp $ */
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/*
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* Copyright (c) 1996, Ignatios Souvatzis.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Ignatios Souvatzis
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* for the NetBSD project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Intel 82595 Ethernet chip register, bit, and structure definitions.
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*
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* Written by is with reference to Intel's i82595FX data sheet, with some
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* clarification coming from looking at the Clarkson Packet Driver code for this
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* chip written by Russ Nelson and others;
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*
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* and
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*
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* configuration EEPROM layout. Written with reference to Intels
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* public "LAN595 Hardware and Software Specifications" document.
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*/
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/* registers */
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/* bank0 */
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#define COMMAND_REG 0 /* available in any bank */
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#define MC_SETUP_CMD 0x03
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#define XMT_CMD 0x04
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#define TDR_CMD 0x05
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#define DUMP_CMD 0x06
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#define DIAG_CMD 0x07
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#define RCV_ENABLE_CMD 0x08
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#define RCV_DISABLE_CMD 0x0a
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#define RCV_STOP_CMD 0x0b
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#define RESET_CMD 0x0e
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#define TRISTATE_CMD 0x16
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#define NO_TRISTATE_CMD 0x17
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#define POWER_DOWN_CMD 0x18
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#define SLEEP_MODE_CMD 0x19
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#define NEGOTIATE_CMD 0x1a
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#define RESUME_XMT_CMD 0x1c
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#define SEL_RESET_CMD 0x1e
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#define BANK_SEL(n) (n<<6) /* 0, 1, 2 */
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#define STATUS_REG 1
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#define RX_STP_INT 0x01
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#define RX_INT 0x02
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#define TX_INT 0x04
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#define EXEC_INT 0x08
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#define EXEC_STATUS 0x30
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#define ID_REG 2
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#define ID_REG_MASK 0x2c
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#define ID_REG_SIG 0x24
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#define R_ROBIN_BITS 0xc0
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#define R_ROBIN_SHIFT 6
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#define AUTO_ENABLE 0x10
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#define INT_MASK_REG 3
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#define RX_STOP_BIT 0x01
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#define RX_BIT 0x02
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#define TX_BIT 0x04
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#define EXEC_BIT 0x08
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#define ALL_INTS 0x0f
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#define RCV_START_LOW 4
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#define RCV_START_HIGH 5
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#define RCV_STOP_LOW 6
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#define RCV_STOP_HIGH 7
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#define XMT_ADDR_REG 0x0a
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#define HOST_ADDR_REG 0x0c
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#define MEM_PORT_REG 0x0e
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/* -------------------- bank1 -------------------- */
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#define REG1 1
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#define WORD_WIDTH 0x02
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#define INT_ENABLE 0x80
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#define INT_NO_REG 2
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#define RCV_LOWER_LIMIT_REG 8
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#define RCV_UPPER_LIMIT_REG 9
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#define XMT_LOWER_LIMIT_REG 10
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#define XMT_UPPER_LIMIT_REG 11
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/* bank2 */
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/* reg1, apparently */
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#define XMT_CHAIN_INT 0x20 /* interupt at end of xmt chain */
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#define XMT_CHAIN_ERRSTOP 0x40 /* int at end of chain even if err */
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#define RCV_DISCARD_BAD 0x80 /* Throw bad frames away and continue */
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#define RECV_MODES_REG 2
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#define PROMISC_MODE 0x01
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#define NO_RX_CRC 0x04
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#define NO_ADD_INS 0x10
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#define MULTI_IA 0x20
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#define MATCH_ID (NO_ADD_INS | NO_RX_CRC | 0x02)
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#define MATCH_ALL (NO_ADD_INS | NO_RX_CRC | 0x01)
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#define MATCH_BRDCST (NO_ADD_INS | NO_RX_CRC)
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#define MEDIA_SELECT 3
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#define TPE_BIT 0x04
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#define BNC_BIT 0x20
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#define TEST_MODE_MASK 0x3f
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#define I_ADD(n) (n+4) /* 0..5 -> 4..9 */
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#define EEPROM_REG 10
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#define EEDO 8
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#define EEDI 4
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#define EECS 2
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#define EESK 1
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/*
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* EEPROM layout. Written with reference to Intels public "LAN595 Hardware and
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* Software Specifications" document.
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*/
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#define EEPPW0 0
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#define EEPP_BusWidth 0x0004
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#define EEPP_FlashAdrs 0x0038
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#define EEPP_FLASHTRANSFORM {-1, -1, 0xC8000, 0xCC000, 0xD0000, \
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0xD4000, 0xD8000, 0xDC000}
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#define EEPP_AutoIO 0x0040
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#define EEPP_IOMapping 0xfc00
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#define EEPPW1 1
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#define EEPP_Int 0x0007
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#define EEPP_INTMAP {3, 5, 9, 10, 11, -1, -1, -1}
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#define EEPP_RINTMAP {0xff, 0xff, 0x02, 0x00, 0xff, 0x01, 0xff, \
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0xff, 0xff, 0x02, 0x03, 0x04 }
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#define EEPP_LinkInteg 0x0008
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#define EEPP_PolarCorr 0x0010
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#define EEPP_AuiTpe 0x0020
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#define EEPP_Jabber 0x0040
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#define EEPP_AutoPort 0x0080
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#define EEPP_SmOut 0x0100
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#define EEPP_BootFls 0x0200
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#define EEPP_DramSize 0x1000
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#define EEPP_AltReady 0x2000
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#define EEPPEther2 2
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#define EEPPEther1 3
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#define EEPPEther0 4
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#define EEPPEther2a 0x3c
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#define EEPPEther1a 0x3d
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#define EEPPEther0a 0x3e
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#define EEPPW5 5
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#define EEPP_BncTpe 0x0001
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#define EEPP_RomSlct 0x0006 /* none, NetWare, NDIS, rsrvd. */
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#define EEPP_NumConn 0x0008 /* 0=2, 1=3 */
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#define EEPW6 6
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#define EEPP_BoardRev 0x00FF
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#define EEPP_LENGTH 0x40
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#define EEPP_CHKSUM 0xBABA /* Intel claim 0x0, but this seems to be wrong */
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#define I595_XMT_HDRLEN 8
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#define CMD_MASK 0x001f
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#define TX_DONE 0x0080
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#define CHAIN 0x8000
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#define XMT_STATUS 0x02
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#define XMT_CHAIN 0x04
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#define XMT_COUNT 0x06
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#define I595_RCV_HDRLEN 8
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#define RCV_DONE 0x0008
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#define RX_OK 0x2000
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#define RX_ERR 0x0d81
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