838 lines
21 KiB
C
838 lines
21 KiB
C
/* $NetBSD: if_qe.c,v 1.51 2002/06/08 12:28:37 ragge Exp $ */
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/*
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* Copyright (c) 1999 Ludd, University of Lule}, Sweden. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed at Ludd, University of
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* Lule}, Sweden and its contributors.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Driver for DEQNA/DELQA ethernet cards.
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* Things that is still to do:
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* Handle ubaresets. Does not work at all right now.
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* Fix ALLMULTI reception. But someone must tell me how...
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* Collect statistics.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_qe.c,v 1.51 2002/06/08 12:28:37 ragge Exp $");
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#include "opt_inet.h"
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#include "bpfilter.h"
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#include <sys/param.h>
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#include <sys/mbuf.h>
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#include <sys/socket.h>
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#include <sys/device.h>
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#include <sys/systm.h>
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#include <sys/sockio.h>
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#include <net/if.h>
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#include <net/if_ether.h>
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#include <net/if_dl.h>
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#include <netinet/in.h>
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#include <netinet/if_inarp.h>
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#if NBPFILTER > 0
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#include <net/bpf.h>
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#include <net/bpfdesc.h>
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#endif
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#include <machine/bus.h>
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#include <dev/qbus/ubavar.h>
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#include <dev/qbus/if_qereg.h>
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#include "ioconf.h"
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#define RXDESCS 30 /* # of receive descriptors */
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#define TXDESCS 60 /* # transmit descs */
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/*
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* Structure containing the elements that must be in DMA-safe memory.
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*/
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struct qe_cdata {
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struct qe_ring qc_recv[RXDESCS+1]; /* Receive descriptors */
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struct qe_ring qc_xmit[TXDESCS+1]; /* Transmit descriptors */
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u_int8_t qc_setup[128]; /* Setup packet layout */
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};
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struct qe_softc {
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struct device sc_dev; /* Configuration common part */
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struct evcnt sc_intrcnt; /* Interrupt counting */
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struct ethercom sc_ec; /* Ethernet common part */
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#define sc_if sc_ec.ec_if /* network-visible interface */
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bus_space_tag_t sc_iot;
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bus_addr_t sc_ioh;
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bus_dma_tag_t sc_dmat;
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struct qe_cdata *sc_qedata; /* Descriptor struct */
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struct qe_cdata *sc_pqedata; /* Unibus address of above */
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struct mbuf* sc_txmbuf[TXDESCS];
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struct mbuf* sc_rxmbuf[RXDESCS];
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bus_dmamap_t sc_xmtmap[TXDESCS];
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bus_dmamap_t sc_rcvmap[RXDESCS];
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struct ubinfo sc_ui;
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int sc_intvec; /* Interrupt vector */
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int sc_nexttx;
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int sc_inq;
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int sc_lastack;
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int sc_nextrx;
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int sc_setup; /* Setup packet in queue */
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};
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static int qematch(struct device *, struct cfdata *, void *);
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static void qeattach(struct device *, struct device *, void *);
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static void qeinit(struct qe_softc *);
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static void qestart(struct ifnet *);
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static void qeintr(void *);
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static int qeioctl(struct ifnet *, u_long, caddr_t);
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static int qe_add_rxbuf(struct qe_softc *, int);
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static void qe_setup(struct qe_softc *);
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static void qetimeout(struct ifnet *);
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struct cfattach qe_ca = {
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sizeof(struct qe_softc), qematch, qeattach
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};
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#define QE_WCSR(csr, val) \
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bus_space_write_2(sc->sc_iot, sc->sc_ioh, csr, val)
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#define QE_RCSR(csr) \
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bus_space_read_2(sc->sc_iot, sc->sc_ioh, csr)
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#define LOWORD(x) ((int)(x) & 0xffff)
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#define HIWORD(x) (((int)(x) >> 16) & 0x3f)
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/*
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* Check for present DEQNA. Done by sending a fake setup packet
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* and wait for interrupt.
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*/
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int
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qematch(struct device *parent, struct cfdata *cf, void *aux)
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{
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struct qe_softc ssc;
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struct qe_softc *sc = &ssc;
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struct uba_attach_args *ua = aux;
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struct uba_softc *ubasc = (struct uba_softc *)parent;
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struct ubinfo ui;
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#define PROBESIZE 4096
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struct qe_ring *ring;
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struct qe_ring *rp;
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int error;
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ring = malloc(PROBESIZE, M_TEMP, M_WAITOK);
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bzero(sc, sizeof(struct qe_softc));
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bzero(ring, PROBESIZE);
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sc->sc_iot = ua->ua_iot;
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sc->sc_ioh = ua->ua_ioh;
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sc->sc_dmat = ua->ua_dmat;
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ubasc->uh_lastiv -= 4;
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QE_WCSR(QE_CSR_CSR, QE_RESET);
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QE_WCSR(QE_CSR_VECTOR, ubasc->uh_lastiv);
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/*
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* Map the ring area. Actually this is done only to be able to
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* send and receive a internal packet; some junk is loopbacked
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* so that the DEQNA has a reason to interrupt.
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*/
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ui.ui_size = PROBESIZE;
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ui.ui_vaddr = (caddr_t)&ring[0];
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if ((error = uballoc((void *)parent, &ui, UBA_CANTWAIT)))
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return 0;
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/*
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* Init a simple "fake" receive and transmit descriptor that
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* points to some unused area. Send a fake setup packet.
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*/
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rp = (void *)ui.ui_baddr;
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ring[0].qe_flag = ring[0].qe_status1 = QE_NOTYET;
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ring[0].qe_addr_lo = LOWORD(&rp[4]);
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ring[0].qe_addr_hi = HIWORD(&rp[4]) | QE_VALID | QE_EOMSG | QE_SETUP;
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ring[0].qe_buf_len = -64;
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ring[2].qe_flag = ring[2].qe_status1 = QE_NOTYET;
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ring[2].qe_addr_lo = LOWORD(&rp[4]);
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ring[2].qe_addr_hi = HIWORD(&rp[4]) | QE_VALID;
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ring[2].qe_buf_len = -(1500/2);
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QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) & ~QE_RESET);
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DELAY(1000);
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/*
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* Start the interface and wait for the packet.
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*/
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QE_WCSR(QE_CSR_CSR, QE_INT_ENABLE|QE_XMIT_INT|QE_RCV_INT);
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QE_WCSR(QE_CSR_RCLL, LOWORD(&rp[2]));
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QE_WCSR(QE_CSR_RCLH, HIWORD(&rp[2]));
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QE_WCSR(QE_CSR_XMTL, LOWORD(rp));
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QE_WCSR(QE_CSR_XMTH, HIWORD(rp));
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DELAY(10000);
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/*
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* All done with the bus resources.
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*/
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ubfree((void *)parent, &ui);
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free(ring, M_TEMP);
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return 1;
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}
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/*
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* Interface exists: make available by filling in network interface
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* record. System will initialize the interface when it is ready
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* to accept packets.
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*/
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void
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qeattach(struct device *parent, struct device *self, void *aux)
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{
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struct uba_attach_args *ua = aux;
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struct uba_softc *ubasc = (struct uba_softc *)parent;
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struct qe_softc *sc = (struct qe_softc *)self;
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struct ifnet *ifp = (struct ifnet *)&sc->sc_if;
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struct qe_ring *rp;
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u_int8_t enaddr[ETHER_ADDR_LEN];
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int i, error;
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sc->sc_iot = ua->ua_iot;
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sc->sc_ioh = ua->ua_ioh;
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sc->sc_dmat = ua->ua_dmat;
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/*
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* Allocate DMA safe memory for descriptors and setup memory.
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*/
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sc->sc_ui.ui_size = sizeof(struct qe_cdata);
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if ((error = ubmemalloc((struct uba_softc *)parent, &sc->sc_ui, 0))) {
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printf(": unable to ubmemalloc(), error = %d\n", error);
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return;
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}
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sc->sc_pqedata = (struct qe_cdata *)sc->sc_ui.ui_baddr;
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sc->sc_qedata = (struct qe_cdata *)sc->sc_ui.ui_vaddr;
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/*
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* Zero the newly allocated memory.
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*/
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bzero(sc->sc_qedata, sizeof(struct qe_cdata));
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/*
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* Create the transmit descriptor DMA maps. We take advantage
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* of the fact that the Qbus address space is big, and therefore
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* allocate map registers for all transmit descriptors also,
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* so that we can avoid this each time we send a packet.
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*/
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for (i = 0; i < TXDESCS; i++) {
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if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
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1, MCLBYTES, 0, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW,
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&sc->sc_xmtmap[i]))) {
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printf(": unable to create tx DMA map %d, error = %d\n",
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i, error);
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goto fail_4;
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}
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}
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/*
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* Create receive buffer DMA maps.
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*/
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for (i = 0; i < RXDESCS; i++) {
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if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
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MCLBYTES, 0, BUS_DMA_NOWAIT,
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&sc->sc_rcvmap[i]))) {
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printf(": unable to create rx DMA map %d, error = %d\n",
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i, error);
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goto fail_5;
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}
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}
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/*
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* Pre-allocate the receive buffers.
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*/
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for (i = 0; i < RXDESCS; i++) {
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if ((error = qe_add_rxbuf(sc, i)) != 0) {
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printf(": unable to allocate or map rx buffer %d\n,"
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" error = %d\n", i, error);
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goto fail_6;
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}
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}
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/*
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* Create ring loops of the buffer chains.
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* This is only done once.
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*/
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rp = sc->sc_qedata->qc_recv;
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rp[RXDESCS].qe_addr_lo = LOWORD(&sc->sc_pqedata->qc_recv[0]);
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rp[RXDESCS].qe_addr_hi = HIWORD(&sc->sc_pqedata->qc_recv[0]) |
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QE_VALID | QE_CHAIN;
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rp[RXDESCS].qe_flag = rp[RXDESCS].qe_status1 = QE_NOTYET;
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rp = sc->sc_qedata->qc_xmit;
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rp[TXDESCS].qe_addr_lo = LOWORD(&sc->sc_pqedata->qc_xmit[0]);
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rp[TXDESCS].qe_addr_hi = HIWORD(&sc->sc_pqedata->qc_xmit[0]) |
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QE_VALID | QE_CHAIN;
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rp[TXDESCS].qe_flag = rp[TXDESCS].qe_status1 = QE_NOTYET;
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/*
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* Get the vector that were set at match time, and remember it.
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*/
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sc->sc_intvec = ubasc->uh_lastiv;
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QE_WCSR(QE_CSR_CSR, QE_RESET);
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DELAY(1000);
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QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) & ~QE_RESET);
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/*
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* Read out ethernet address and tell which type this card is.
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*/
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for (i = 0; i < 6; i++)
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enaddr[i] = QE_RCSR(i * 2) & 0xff;
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QE_WCSR(QE_CSR_VECTOR, sc->sc_intvec | 1);
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printf("\n%s: %s, hardware address %s\n", sc->sc_dev.dv_xname,
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QE_RCSR(QE_CSR_VECTOR) & 1 ? "delqa":"deqna",
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ether_sprintf(enaddr));
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QE_WCSR(QE_CSR_VECTOR, QE_RCSR(QE_CSR_VECTOR) & ~1); /* ??? */
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uba_intr_establish(ua->ua_icookie, ua->ua_cvec, qeintr,
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sc, &sc->sc_intrcnt);
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evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt,
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sc->sc_dev.dv_xname, "intr");
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strcpy(ifp->if_xname, sc->sc_dev.dv_xname);
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ifp->if_softc = sc;
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ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
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ifp->if_start = qestart;
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ifp->if_ioctl = qeioctl;
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ifp->if_watchdog = qetimeout;
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IFQ_SET_READY(&ifp->if_snd);
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/*
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* Attach the interface.
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*/
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if_attach(ifp);
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ether_ifattach(ifp, enaddr);
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return;
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/*
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* Free any resources we've allocated during the failed attach
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* attempt. Do this in reverse order and fall through.
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*/
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fail_6:
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for (i = 0; i < RXDESCS; i++) {
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if (sc->sc_rxmbuf[i] != NULL) {
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bus_dmamap_unload(sc->sc_dmat, sc->sc_xmtmap[i]);
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m_freem(sc->sc_rxmbuf[i]);
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}
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}
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fail_5:
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for (i = 0; i < RXDESCS; i++) {
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if (sc->sc_xmtmap[i] != NULL)
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bus_dmamap_destroy(sc->sc_dmat, sc->sc_xmtmap[i]);
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}
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fail_4:
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for (i = 0; i < TXDESCS; i++) {
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if (sc->sc_rcvmap[i] != NULL)
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bus_dmamap_destroy(sc->sc_dmat, sc->sc_rcvmap[i]);
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}
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}
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/*
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* Initialization of interface.
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*/
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void
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qeinit(struct qe_softc *sc)
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{
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struct ifnet *ifp = (struct ifnet *)&sc->sc_if;
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struct qe_cdata *qc = sc->sc_qedata;
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int i;
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/*
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* Reset the interface.
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*/
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QE_WCSR(QE_CSR_CSR, QE_RESET);
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DELAY(1000);
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QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) & ~QE_RESET);
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QE_WCSR(QE_CSR_VECTOR, sc->sc_intvec);
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sc->sc_nexttx = sc->sc_inq = sc->sc_lastack = 0;
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/*
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* Release and init transmit descriptors.
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*/
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for (i = 0; i < TXDESCS; i++) {
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if (sc->sc_txmbuf[i]) {
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bus_dmamap_unload(sc->sc_dmat, sc->sc_xmtmap[i]);
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m_freem(sc->sc_txmbuf[i]);
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sc->sc_txmbuf[i] = 0;
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}
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qc->qc_xmit[i].qe_addr_hi = 0; /* Clear valid bit */
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qc->qc_xmit[i].qe_status1 = qc->qc_xmit[i].qe_flag = QE_NOTYET;
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}
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/*
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* Init receive descriptors.
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*/
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for (i = 0; i < RXDESCS; i++)
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qc->qc_recv[i].qe_status1 = qc->qc_recv[i].qe_flag = QE_NOTYET;
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sc->sc_nextrx = 0;
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/*
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* Write the descriptor addresses to the device.
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* Receiving packets will be enabled in the interrupt routine.
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*/
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QE_WCSR(QE_CSR_CSR, QE_INT_ENABLE|QE_XMIT_INT|QE_RCV_INT);
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QE_WCSR(QE_CSR_RCLL, LOWORD(sc->sc_pqedata->qc_recv));
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QE_WCSR(QE_CSR_RCLH, HIWORD(sc->sc_pqedata->qc_recv));
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ifp->if_flags |= IFF_RUNNING;
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ifp->if_flags &= ~IFF_OACTIVE;
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/*
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* Send a setup frame.
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* This will start the transmit machinery as well.
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*/
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qe_setup(sc);
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}
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/*
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* Start output on interface.
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*/
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void
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qestart(struct ifnet *ifp)
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{
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struct qe_softc *sc = ifp->if_softc;
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struct qe_cdata *qc = sc->sc_qedata;
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paddr_t buffer;
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struct mbuf *m, *m0;
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int idx, len, s, i, totlen, error;
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short orword, csr;
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if ((QE_RCSR(QE_CSR_CSR) & QE_RCV_ENABLE) == 0)
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return;
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s = splnet();
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while (sc->sc_inq < (TXDESCS - 1)) {
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if (sc->sc_setup) {
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qe_setup(sc);
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continue;
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}
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idx = sc->sc_nexttx;
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IFQ_POLL(&ifp->if_snd, m);
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if (m == 0)
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goto out;
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/*
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* Count number of mbufs in chain.
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* Always do DMA directly from mbufs, therefore the transmit
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* ring is really big.
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*/
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for (m0 = m, i = 0; m0; m0 = m0->m_next)
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if (m0->m_len)
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i++;
|
|
if (i >= TXDESCS)
|
|
panic("qestart");
|
|
|
|
if ((i + sc->sc_inq) >= (TXDESCS - 1)) {
|
|
ifp->if_flags |= IFF_OACTIVE;
|
|
goto out;
|
|
}
|
|
|
|
IFQ_DEQUEUE(&ifp->if_snd, m);
|
|
|
|
#if NBPFILTER > 0
|
|
if (ifp->if_bpf)
|
|
bpf_mtap(ifp->if_bpf, m);
|
|
#endif
|
|
/*
|
|
* m now points to a mbuf chain that can be loaded.
|
|
* Loop around and set it.
|
|
*/
|
|
totlen = 0;
|
|
for (m0 = m; m0; m0 = m0->m_next) {
|
|
error = bus_dmamap_load(sc->sc_dmat, sc->sc_xmtmap[idx],
|
|
mtod(m0, void *), m0->m_len, 0, 0);
|
|
buffer = sc->sc_xmtmap[idx]->dm_segs[0].ds_addr;
|
|
len = m0->m_len;
|
|
if (len == 0)
|
|
continue;
|
|
|
|
totlen += len;
|
|
/* Word alignment calc */
|
|
orword = 0;
|
|
if (totlen == m->m_pkthdr.len) {
|
|
if (totlen < ETHER_MIN_LEN)
|
|
len += (ETHER_MIN_LEN - totlen);
|
|
orword |= QE_EOMSG;
|
|
sc->sc_txmbuf[idx] = m;
|
|
}
|
|
if ((buffer & 1) || (len & 1))
|
|
len += 2;
|
|
if (buffer & 1)
|
|
orword |= QE_ODDBEGIN;
|
|
if ((buffer + len) & 1)
|
|
orword |= QE_ODDEND;
|
|
qc->qc_xmit[idx].qe_buf_len = -(len/2);
|
|
qc->qc_xmit[idx].qe_addr_lo = LOWORD(buffer);
|
|
qc->qc_xmit[idx].qe_addr_hi = HIWORD(buffer);
|
|
qc->qc_xmit[idx].qe_flag =
|
|
qc->qc_xmit[idx].qe_status1 = QE_NOTYET;
|
|
qc->qc_xmit[idx].qe_addr_hi |= (QE_VALID | orword);
|
|
if (++idx == TXDESCS)
|
|
idx = 0;
|
|
sc->sc_inq++;
|
|
}
|
|
#ifdef DIAGNOSTIC
|
|
if (totlen != m->m_pkthdr.len)
|
|
panic("qestart: len fault");
|
|
#endif
|
|
|
|
/*
|
|
* Kick off the transmit logic, if it is stopped.
|
|
*/
|
|
csr = QE_RCSR(QE_CSR_CSR);
|
|
if (csr & QE_XL_INVALID) {
|
|
QE_WCSR(QE_CSR_XMTL,
|
|
LOWORD(&sc->sc_pqedata->qc_xmit[sc->sc_nexttx]));
|
|
QE_WCSR(QE_CSR_XMTH,
|
|
HIWORD(&sc->sc_pqedata->qc_xmit[sc->sc_nexttx]));
|
|
}
|
|
sc->sc_nexttx = idx;
|
|
}
|
|
if (sc->sc_inq == (TXDESCS - 1))
|
|
ifp->if_flags |= IFF_OACTIVE;
|
|
|
|
out: if (sc->sc_inq)
|
|
ifp->if_timer = 5; /* If transmit logic dies */
|
|
splx(s);
|
|
}
|
|
|
|
static void
|
|
qeintr(void *arg)
|
|
{
|
|
struct qe_softc *sc = arg;
|
|
struct qe_cdata *qc = sc->sc_qedata;
|
|
struct ifnet *ifp = &sc->sc_if;
|
|
struct mbuf *m;
|
|
int csr, status1, status2, len;
|
|
|
|
csr = QE_RCSR(QE_CSR_CSR);
|
|
|
|
QE_WCSR(QE_CSR_CSR, QE_RCV_ENABLE | QE_INT_ENABLE | QE_XMIT_INT |
|
|
QE_RCV_INT | QE_ILOOP);
|
|
|
|
if (csr & QE_RCV_INT)
|
|
while (qc->qc_recv[sc->sc_nextrx].qe_status1 != QE_NOTYET) {
|
|
status1 = qc->qc_recv[sc->sc_nextrx].qe_status1;
|
|
status2 = qc->qc_recv[sc->sc_nextrx].qe_status2;
|
|
|
|
m = sc->sc_rxmbuf[sc->sc_nextrx];
|
|
len = ((status1 & QE_RBL_HI) |
|
|
(status2 & QE_RBL_LO)) + 60;
|
|
qe_add_rxbuf(sc, sc->sc_nextrx);
|
|
m->m_pkthdr.rcvif = ifp;
|
|
m->m_pkthdr.len = m->m_len = len;
|
|
if (++sc->sc_nextrx == RXDESCS)
|
|
sc->sc_nextrx = 0;
|
|
#if NBPFILTER > 0
|
|
if (ifp->if_bpf)
|
|
bpf_mtap(ifp->if_bpf, m);
|
|
#endif
|
|
if ((status1 & QE_ESETUP) == 0)
|
|
(*ifp->if_input)(ifp, m);
|
|
else
|
|
m_freem(m);
|
|
}
|
|
|
|
if (csr & (QE_XMIT_INT|QE_XL_INVALID)) {
|
|
while (qc->qc_xmit[sc->sc_lastack].qe_status1 != QE_NOTYET) {
|
|
int idx = sc->sc_lastack;
|
|
|
|
sc->sc_inq--;
|
|
if (++sc->sc_lastack == TXDESCS)
|
|
sc->sc_lastack = 0;
|
|
|
|
/* XXX collect statistics */
|
|
qc->qc_xmit[idx].qe_addr_hi &= ~QE_VALID;
|
|
qc->qc_xmit[idx].qe_status1 =
|
|
qc->qc_xmit[idx].qe_flag = QE_NOTYET;
|
|
|
|
if (qc->qc_xmit[idx].qe_addr_hi & QE_SETUP)
|
|
continue;
|
|
bus_dmamap_unload(sc->sc_dmat, sc->sc_xmtmap[idx]);
|
|
if (sc->sc_txmbuf[idx]) {
|
|
m_freem(sc->sc_txmbuf[idx]);
|
|
sc->sc_txmbuf[idx] = 0;
|
|
}
|
|
}
|
|
ifp->if_timer = 0;
|
|
ifp->if_flags &= ~IFF_OACTIVE;
|
|
qestart(ifp); /* Put in more in queue */
|
|
}
|
|
/*
|
|
* How can the receive list get invalid???
|
|
* Verified that it happens anyway.
|
|
*/
|
|
if ((qc->qc_recv[sc->sc_nextrx].qe_status1 == QE_NOTYET) &&
|
|
(QE_RCSR(QE_CSR_CSR) & QE_RL_INVALID)) {
|
|
QE_WCSR(QE_CSR_RCLL,
|
|
LOWORD(&sc->sc_pqedata->qc_recv[sc->sc_nextrx]));
|
|
QE_WCSR(QE_CSR_RCLH,
|
|
HIWORD(&sc->sc_pqedata->qc_recv[sc->sc_nextrx]));
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Process an ioctl request.
|
|
*/
|
|
int
|
|
qeioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
|
|
{
|
|
struct qe_softc *sc = ifp->if_softc;
|
|
struct ifreq *ifr = (struct ifreq *)data;
|
|
struct ifaddr *ifa = (struct ifaddr *)data;
|
|
int s = splnet(), error = 0;
|
|
|
|
switch (cmd) {
|
|
|
|
case SIOCSIFADDR:
|
|
ifp->if_flags |= IFF_UP;
|
|
switch(ifa->ifa_addr->sa_family) {
|
|
#ifdef INET
|
|
case AF_INET:
|
|
qeinit(sc);
|
|
arp_ifinit(ifp, ifa);
|
|
break;
|
|
#endif
|
|
}
|
|
break;
|
|
|
|
case SIOCSIFFLAGS:
|
|
if ((ifp->if_flags & IFF_UP) == 0 &&
|
|
(ifp->if_flags & IFF_RUNNING) != 0) {
|
|
/*
|
|
* If interface is marked down and it is running,
|
|
* stop it. (by disabling receive mechanism).
|
|
*/
|
|
QE_WCSR(QE_CSR_CSR,
|
|
QE_RCSR(QE_CSR_CSR) & ~QE_RCV_ENABLE);
|
|
ifp->if_flags &= ~IFF_RUNNING;
|
|
} else if ((ifp->if_flags & IFF_UP) != 0 &&
|
|
(ifp->if_flags & IFF_RUNNING) == 0) {
|
|
/*
|
|
* If interface it marked up and it is stopped, then
|
|
* start it.
|
|
*/
|
|
qeinit(sc);
|
|
} else if ((ifp->if_flags & IFF_UP) != 0) {
|
|
/*
|
|
* Send a new setup packet to match any new changes.
|
|
* (Like IFF_PROMISC etc)
|
|
*/
|
|
qe_setup(sc);
|
|
}
|
|
break;
|
|
|
|
case SIOCADDMULTI:
|
|
case SIOCDELMULTI:
|
|
/*
|
|
* Update our multicast list.
|
|
*/
|
|
error = (cmd == SIOCADDMULTI) ?
|
|
ether_addmulti(ifr, &sc->sc_ec):
|
|
ether_delmulti(ifr, &sc->sc_ec);
|
|
|
|
if (error == ENETRESET) {
|
|
/*
|
|
* Multicast list has changed; set the hardware filter
|
|
* accordingly.
|
|
*/
|
|
qe_setup(sc);
|
|
error = 0;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
error = EINVAL;
|
|
|
|
}
|
|
splx(s);
|
|
return (error);
|
|
}
|
|
|
|
/*
|
|
* Add a receive buffer to the indicated descriptor.
|
|
*/
|
|
int
|
|
qe_add_rxbuf(struct qe_softc *sc, int i)
|
|
{
|
|
struct mbuf *m;
|
|
struct qe_ring *rp;
|
|
vaddr_t addr;
|
|
int error;
|
|
|
|
MGETHDR(m, M_DONTWAIT, MT_DATA);
|
|
if (m == NULL)
|
|
return (ENOBUFS);
|
|
|
|
MCLGET(m, M_DONTWAIT);
|
|
if ((m->m_flags & M_EXT) == 0) {
|
|
m_freem(m);
|
|
return (ENOBUFS);
|
|
}
|
|
|
|
if (sc->sc_rxmbuf[i] != NULL)
|
|
bus_dmamap_unload(sc->sc_dmat, sc->sc_rcvmap[i]);
|
|
|
|
error = bus_dmamap_load(sc->sc_dmat, sc->sc_rcvmap[i],
|
|
m->m_ext.ext_buf, m->m_ext.ext_size, NULL, BUS_DMA_NOWAIT);
|
|
if (error)
|
|
panic("%s: can't load rx DMA map %d, error = %d\n",
|
|
sc->sc_dev.dv_xname, i, error);
|
|
sc->sc_rxmbuf[i] = m;
|
|
|
|
bus_dmamap_sync(sc->sc_dmat, sc->sc_rcvmap[i], 0,
|
|
sc->sc_rcvmap[i]->dm_mapsize, BUS_DMASYNC_PREREAD);
|
|
|
|
/*
|
|
* We know that the mbuf cluster is page aligned. Also, be sure
|
|
* that the IP header will be longword aligned.
|
|
*/
|
|
m->m_data += 2;
|
|
addr = sc->sc_rcvmap[i]->dm_segs[0].ds_addr + 2;
|
|
rp = &sc->sc_qedata->qc_recv[i];
|
|
rp->qe_flag = rp->qe_status1 = QE_NOTYET;
|
|
rp->qe_addr_lo = LOWORD(addr);
|
|
rp->qe_addr_hi = HIWORD(addr) | QE_VALID;
|
|
rp->qe_buf_len = -(m->m_ext.ext_size - 2)/2;
|
|
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* Create a setup packet and put in queue for sending.
|
|
*/
|
|
void
|
|
qe_setup(struct qe_softc *sc)
|
|
{
|
|
struct ether_multi *enm;
|
|
struct ether_multistep step;
|
|
struct qe_cdata *qc = sc->sc_qedata;
|
|
struct ifnet *ifp = &sc->sc_if;
|
|
u_int8_t *enaddr = LLADDR(ifp->if_sadl);
|
|
int i, j, k, idx, s;
|
|
|
|
s = splnet();
|
|
if (sc->sc_inq == (TXDESCS - 1)) {
|
|
sc->sc_setup = 1;
|
|
splx(s);
|
|
return;
|
|
}
|
|
sc->sc_setup = 0;
|
|
/*
|
|
* Init the setup packet with valid info.
|
|
*/
|
|
memset(qc->qc_setup, 0xff, sizeof(qc->qc_setup)); /* Broadcast */
|
|
for (i = 0; i < ETHER_ADDR_LEN; i++)
|
|
qc->qc_setup[i * 8 + 1] = enaddr[i]; /* Own address */
|
|
|
|
/*
|
|
* Multicast handling. The DEQNA can handle up to 12 direct
|
|
* ethernet addresses.
|
|
*/
|
|
j = 3; k = 0;
|
|
ifp->if_flags &= ~IFF_ALLMULTI;
|
|
ETHER_FIRST_MULTI(step, &sc->sc_ec, enm);
|
|
while (enm != NULL) {
|
|
if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6)) {
|
|
ifp->if_flags |= IFF_ALLMULTI;
|
|
break;
|
|
}
|
|
for (i = 0; i < ETHER_ADDR_LEN; i++)
|
|
qc->qc_setup[i * 8 + j + k] = enm->enm_addrlo[i];
|
|
j++;
|
|
if (j == 8) {
|
|
j = 1; k += 64;
|
|
}
|
|
if (k > 64) {
|
|
ifp->if_flags |= IFF_ALLMULTI;
|
|
break;
|
|
}
|
|
ETHER_NEXT_MULTI(step, enm);
|
|
}
|
|
idx = sc->sc_nexttx;
|
|
qc->qc_xmit[idx].qe_buf_len = -64;
|
|
|
|
/*
|
|
* How is the DEQNA turned in ALLMULTI mode???
|
|
* Until someone tells me, fall back to PROMISC when more than
|
|
* 12 ethernet addresses.
|
|
*/
|
|
if (ifp->if_flags & IFF_ALLMULTI)
|
|
ifp->if_flags |= IFF_PROMISC;
|
|
else if (ifp->if_pcount == 0)
|
|
ifp->if_flags &= ~IFF_PROMISC;
|
|
if (ifp->if_flags & IFF_PROMISC)
|
|
qc->qc_xmit[idx].qe_buf_len = -65;
|
|
|
|
qc->qc_xmit[idx].qe_addr_lo = LOWORD(sc->sc_pqedata->qc_setup);
|
|
qc->qc_xmit[idx].qe_addr_hi =
|
|
HIWORD(sc->sc_pqedata->qc_setup) | QE_SETUP | QE_EOMSG;
|
|
qc->qc_xmit[idx].qe_status1 = qc->qc_xmit[idx].qe_flag = QE_NOTYET;
|
|
qc->qc_xmit[idx].qe_addr_hi |= QE_VALID;
|
|
|
|
if (QE_RCSR(QE_CSR_CSR) & QE_XL_INVALID) {
|
|
QE_WCSR(QE_CSR_XMTL,
|
|
LOWORD(&sc->sc_pqedata->qc_xmit[idx]));
|
|
QE_WCSR(QE_CSR_XMTH,
|
|
HIWORD(&sc->sc_pqedata->qc_xmit[idx]));
|
|
}
|
|
|
|
sc->sc_inq++;
|
|
if (++sc->sc_nexttx == TXDESCS)
|
|
sc->sc_nexttx = 0;
|
|
splx(s);
|
|
}
|
|
|
|
/*
|
|
* Check for dead transmit logic. Not uncommon.
|
|
*/
|
|
void
|
|
qetimeout(struct ifnet *ifp)
|
|
{
|
|
struct qe_softc *sc = ifp->if_softc;
|
|
|
|
if (sc->sc_inq == 0)
|
|
return;
|
|
|
|
printf("%s: xmit logic died, resetting...\n", sc->sc_dev.dv_xname);
|
|
/*
|
|
* Do a reset of interface, to get it going again.
|
|
* Will it work by just restart the transmit logic?
|
|
*/
|
|
qeinit(sc);
|
|
}
|