230 lines
9.1 KiB
C
230 lines
9.1 KiB
C
/* $NetBSD: hd64461pcmciareg.h,v 1.2 2001/10/08 15:34:24 uch Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* PCC0 SH7709 Area 6 (memory and I/O card)
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*/
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/* PCC0 Interface Status Register (R) */
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#define HD64461_PCC0ISR_REG8 0xb0002000
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#define HD64461_PCC0ISR_P0READY HD64461_PCCISR_READY
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#define HD64461_PCC0ISR_IREQ HD64461_PCCISR_READY
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#define HD64461_PCC0ISR_P0MWP HD64461_PCCISR_MWP
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#define HD64461_PCC0ISR_P0VS2 HD64461_PCCISR_VS2
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#define HD64461_PCC0ISR_P0VS1 HD64461_PCCISR_VS1
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#define HD64461_PCC0ISR_P0CD2 HD64461_PCCISR_CD2
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#define HD64461_PCC0ISR_P0CD1 HD64461_PCCISR_CD1
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#define HD64461_PCC0ISR_P0BVD2 HD64461_PCCISR_BVD2
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#define HD64461_PCC0ISR_SPKR0 HD64461_PCCISR_BVD2
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#define HD64461_PCC0ISR_P0BVD1 HD64461_PCCISR_BVD1
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#define HD64461_PCC0ISR_STSCHG0 HD64461_PCCISR_BVD1
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/* PCC0 General Contorol Register (R/W) */
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#define HD64461_PCC0GCR_REG8 0xb0002002
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#define HD64461_PCC0GCR_P0DRVE HD64461_PCCGCR_DRVE
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#define HD64461_PCC0GCR_P0PCCR HD64461_PCCGCR_PCCR
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#define HD64461_PCC0GCR_P0PCCT HD64461_PCCGCR_PCCT
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#define HD64461_PCC0GCR_P0VCC0 HD64461_PCCGCR_VCC0
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#define HD64461_PCC0GCR_P0MMOD HD64461_PCCGCR_MMOD
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#define HD64461_PCC0GCR_P0MMOD_16M HD64461_PCCGCR_MMOD_16M
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#define HD64461_PCC0GCR_P0MMOD_32M HD64461_PCCGCR_MMOD_32M
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/* these bits meaning different for P0MMOD mode */
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#define HD64461_PCC0GCR_P0PA25 HD64461_PCCGCR_PA25
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#define HD64461_PCC0GCR_P0PA24 HD64461_PCCGCR_PA24
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#define HD64461_PCC0GCR_P0REG HD64461_PCCGCR_PREG
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/* PCC0 Card Status Change Register (R/W) */
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#define HD64461_PCC0CSCR_REG8 0xb0002004
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#define HD64461_PCC0CSCR_P0SCDI HD64461_PCCCSCR_SCDI
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#define HD64461_PCC0CSCR_P0IREQ 0x20
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#define HD64461_PCC0CSCR_P0SC 0x10
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#define HD64461_PCC0CSCR_P0CDC HD64461_PCCCSCR_CDC
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#define HD64461_PCC0CSCR_P0RC HD64461_PCCCSCR_RC
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#define HD64461_PCC0CSCR_P0BW HD64461_PCCCSCR_BW
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#define HD64461_PCC0CSCR_P0BD HD64461_PCCCSCR_BD
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/* PCC0 Card Status Change Interrupt Enable Register (R/W) */
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#define HD64461_PCC0CSCIER_REG8 0xb0002006
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#define HD64461_PCC0CSCIER_P0CRE HD64461_PCCCSCIER_CRE
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#define HD64461_PCC0CSCIER_P0IREQE_MASK 0x60
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#define HD64461_PCC0CSCIER_P0IREQE_NONE 0x00
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#define HD64461_PCC0CSCIER_P0IREQE_LEVEL 0x20
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#define HD64461_PCC0CSCIER_P0IREQE_FEDGE 0x40
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#define HD64461_PCC0CSCIER_P0IREQE_REDGE 0x60
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#define HD64461_PCC0CSCIER_P0SCE 0x10
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#define HD64461_PCC0CSCIER_P0CDE HD64461_PCCCSCIER_CDE
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#define HD64461_PCC0CSCIER_P0RE HD64461_PCCCSCIER_RE
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#define HD64461_PCC0CSCIER_P0BWE HD64461_PCCCSCIER_BWE
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#define HD64461_PCC0CSCIER_P0BDE HD64461_PCCCSCIER_BDE
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/* PCC0 Software Control Register (R/W) */
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#define HD64461_PCC0SCR_REG8 0xb0002008
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#define HD64461_PCC0SCR_P0VCC1 HD64461_PCCSCR_VCC1
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#define HD64461_PCC0SCR_P0SWP HD64461_PCCSCR_SWP
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/*
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* PCC1 SH7709 Area 5 (memory card only)
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*/
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/* PCC1 Interface Status Register (R) */
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#define HD64461_PCC1ISR_REG8 0xb0002010
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#define HD64461_PCC1ISR_P1READY HD64461_PCCISR_READY
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#define HD64461_PCC1ISR_P1MWP HD64461_PCCISR_MWP
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#define HD64461_PCC1ISR_P1VS2 HD64461_PCCISR_VS2
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#define HD64461_PCC1ISR_P1VS1 HD64461_PCCISR_VS1
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#define HD64461_PCC1ISR_P1CD2 HD64461_PCCISR_CD2
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#define HD64461_PCC1ISR_P1CD1 HD64461_PCCISR_CD1
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#define HD64461_PCC1ISR_P1BVD2 HD64461_PCCISR_BVD2
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#define HD64461_PCC1ISR_P1BVD1 HD64461_PCCISR_BVD1
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/* PCC1 General Contorol Register (R/W) */
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#define HD64461_PCC1GCR_REG8 0xb0002012
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#define HD64461_PCC1GCR_P1DRVE HD64461_PCCGCR_DRVE
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#define HD64461_PCC1GCR_P1PCCR HD64461_PCCGCR_PCCR
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#define HD64461_PCC1GCR_RESERVED HD64461_PCCGCR_PCCT
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#define HD64461_PCC1GCR_P1VCC0 HD64461_PCCGCR_VCC0
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#define HD64461_PCC1GCR_P1MMOD HD64461_PCCGCR_MMOD
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#define HD64461_PCC1GCR_P1MMOD_16M HD64461_PCCGCR_MMOD_16M
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#define HD64461_PCC1GCR_P1MMOD_32M HD64461_PCCGCR_MMOD_32M
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#define HD64461_PCC1GCR_P1PA25 HD64461_PCCGCR_PA25
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#define HD64461_PCC1GCR_P1PA24 HD64461_PCCGCR_PA24
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#define HD64461_PCC1GCR_P1REG HD64461_PCCGCR_PREG
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/* PCC1 Card Status Change Register (R/W) */
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#define HD64461_PCC1CSCR_REG8 0xb0002014
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#define HD64461_PCC1CSCR_P1SCDI HD64461_PCCCSCR_SCDI
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#define HD64461_PCC1CSCR_P1CDC HD64461_PCCCSCR_CDC
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#define HD64461_PCC1CSCR_P1RC HD64461_PCCCSCR_RC
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#define HD64461_PCC1CSCR_P1BW HD64461_PCCCSCR_BW
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#define HD64461_PCC1CSCR_P1BD HD64461_PCCCSCR_BD
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/* PCC1 Card Status Change Interrupt Enable Register (R/W) */
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#define HD64461_PCC1CSCIER_REG8 0xb0002016
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#define HD64461_PCC1CSCIER_P1CRE HD64461_PCCCSCIER_CRE
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#define HD64461_PCC1CSCIER_P1CDE HD64461_PCCCSCIER_CDE
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#define HD64461_PCC1CSCIER_P1RE HD64461_PCCCSCIER_RE
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#define HD64461_PCC1CSCIER_P1BWE HD64461_PCCCSCIER_BWE
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#define HD64461_PCC1CSCIER_P1BDE HD64461_PCCCSCIER_BDE
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/* PCC1 Software Control Register (R/W) */
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#define HD64461_PCC1SCR_REG8 0xb0002018
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#define HD64461_PCC1SCR_P1VCC1 HD64461_PCCSCR_VCC1
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#define HD64461_PCC1SCR_P1SWP HD64461_PCCSCR_SWP
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/*
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* General Control
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*/
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/* PCC0 Output pins Control Register (R/W) */
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#define HD64461_PCCP0OCR_REG8 0xb000202a
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#define HD64461_PCCP0OCR_P0DEPLUP 0x80
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#define HD64461_PCCP0OCR_P0AEPLUP 0x10
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/* PCC1 Output pins Control Register (R/W) */
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#define HD64461_PCCP1OCR_REG8 0xb000202c
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#define HD64461_PCCP1OCR_P1RST8MA 0x08
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#define HD64461_PCCP1OCR_P1RST4MA 0x04
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#define HD64461_PCCP1OCR_P1RAS8MA 0x02
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#define HD64461_PCCP1OCR_P1RAS4MA 0x01
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/* PC Card General Control Register (R/W) */
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#define HD64461_PCCPGCR_REG8 0xb000202e
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#define HD64461_PCCPGCR_PSSDIR 0x02
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#define HD64461_PCCPGCR_PSSRDWR 0x01
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/*
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* common defines.
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*/
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#define HD64461_PCC0_REGBASE HD64461_PCC0ISR_REG8
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#define HD64461_PCC1_REGBASE HD64461_PCC1ISR_REG8
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#define HD64461_PCC_ISR_OFS 0x0
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#define HD64461_PCC_GCR_OFS 0x2
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#define HD64461_PCC_CSCR_OFS 0x4
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#define HD64461_PCC_CSCIER_OFS 0x6
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#define HD64461_PCC_SCR_OFS 0x8
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#define HD64461_PCCISR(x) \
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(((x) ? HD64461_PCC1_REGBASE : HD64461_PCC0_REGBASE) + \
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HD64461_PCC_ISR_OFS)
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#define HD64461_PCCGCR(x) \
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(((x) ? HD64461_PCC1_REGBASE : HD64461_PCC0_REGBASE) + \
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HD64461_PCC_GCR_OFS)
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#define HD64461_PCCCSCR(x) \
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(((x) ? HD64461_PCC1_REGBASE : HD64461_PCC0_REGBASE) + \
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HD64461_PCC_CSCR_OFS)
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#define HD64461_PCCCSCIER(x) \
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(((x) ? HD64461_PCC1_REGBASE : HD64461_PCC0_REGBASE) + \
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HD64461_PCC_CSCIER_OFS)
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#define HD64461_PCCSCR(x) \
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(((x) ? HD64461_PCC1_REGBASE : HD64461_PCC0_REGBASE) + \
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HD64461_PCC_SCR_OFS)
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#define HD64461_PCCISR_READY 0x80
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#define HD64461_PCCISR_MWP 0x40
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#define HD64461_PCCISR_VS2 0x20
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#define HD64461_PCCISR_VS1 0x10
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#define HD64461_PCCISR_CD2 0x08
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#define HD64461_PCCISR_CD1 0x04
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#define HD64461_PCCISR_BVD2 0x02
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#define HD64461_PCCISR_BVD1 0x01
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#define HD64461_PCCGCR_DRVE 0x80
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#define HD64461_PCCGCR_PCCR 0x40
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#define HD64461_PCCGCR_PCCT 0x20
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#define HD64461_PCCGCR_VCC0 0x10
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#define HD64461_PCCGCR_MMOD 0x08
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#define HD64461_PCCGCR_MMOD_16M 0x08
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#define HD64461_PCCGCR_MMOD_32M 0x00
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#define HD64461_PCCGCR_PA25 0x04
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#define HD64461_PCCGCR_PA24 0x02
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#define HD64461_PCCGCR_PREG 0x01
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#define HD64461_PCCCSCR_SCDI 0x80
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#define HD64461_PCCCSCR_CDC 0x08
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#define HD64461_PCCCSCR_RC 0x04
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#define HD64461_PCCCSCR_BW 0x02
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#define HD64461_PCCCSCR_BD 0x01
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#define HD64461_PCCCSCIER_CRE 0x80
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#define HD64461_PCCCSCIER_CDE 0x08
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#define HD64461_PCCCSCIER_RE 0x04
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#define HD64461_PCCCSCIER_BWE 0x02
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#define HD64461_PCCCSCIER_BDE 0x01
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#define HD64461_PCCSCR_VCC1 0x02
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#define HD64461_PCCSCR_SWP 0x01
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