542 lines
14 KiB
C
542 lines
14 KiB
C
/* $NetBSD: igphy.c,v 1.37 2020/11/04 09:15:10 msaitoh Exp $ */
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/*
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* The Intel copyright applies to the analog register setup, and the
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* SmartSpeed workaround code.
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*/
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/*******************************************************************************
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Copyright (c) 2001-2003, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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/*-
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* Copyright (c) 1998, 1999, 2000, 2003 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center, and by Frank van der Linden.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: igphy.c,v 1.37 2020/11/04 09:15:10 msaitoh Exp $");
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#ifdef _KERNEL_OPT
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#include "opt_mii.h"
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#endif
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <sys/socket.h>
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#include <sys/errno.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <dev/mii/miidevs.h>
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#include <dev/mii/igphyreg.h>
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#include <dev/mii/igphyvar.h>
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#include <dev/pci/if_wmvar.h>
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static void igphy_reset(struct mii_softc *);
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static void igphy_load_dspcode(struct mii_softc *);
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static void igphy_load_dspcode_igp3(struct mii_softc *);
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static void igphy_smartspeed_workaround(struct mii_softc *sc);
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static int igphymatch(device_t, cfdata_t, void *);
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static void igphyattach(device_t, device_t, void *);
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CFATTACH_DECL_NEW(igphy, sizeof(struct igphy_softc),
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igphymatch, igphyattach, mii_phy_detach, mii_phy_activate);
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static int igphy_service(struct mii_softc *, struct mii_data *, int);
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static void igphy_status(struct mii_softc *);
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static const struct mii_phy_funcs igphy_funcs = {
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igphy_service, igphy_status, igphy_reset,
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};
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static const struct mii_phydesc igphys[] = {
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MII_PHY_DESC(yyINTEL, IGP01E1000),
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MII_PHY_DESC(yyINTEL, I82566),
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MII_PHY_END,
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};
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static int
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igphymatch(device_t parent, cfdata_t match, void *aux)
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{
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struct mii_attach_args *ma = aux;
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if (mii_phy_match(ma, igphys) != NULL)
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return 10;
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return 0;
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}
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static void
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igphyattach(device_t parent, device_t self, void *aux)
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{
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struct mii_softc *sc = device_private(self);
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struct mii_attach_args *ma = aux;
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struct mii_data *mii = ma->mii_data;
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const struct mii_phydesc *mpd;
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struct igphy_softc *igsc = (struct igphy_softc *)sc;
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prop_dictionary_t dict;
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mpd = mii_phy_match(ma, igphys);
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aprint_naive(": Media interface\n");
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aprint_normal(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
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dict = device_properties(parent);
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if (!prop_dictionary_get_uint32(dict, "mactype", &igsc->sc_mactype))
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aprint_error("WARNING! Failed to get mactype\n");
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if (!prop_dictionary_get_uint32(dict, "macflags", &igsc->sc_macflags))
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aprint_error("WARNING! Failed to get macflags\n");
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sc->mii_dev = self;
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sc->mii_inst = mii->mii_instance;
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sc->mii_phy = ma->mii_phyno;
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sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
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sc->mii_mpd_model = MII_MODEL(ma->mii_id2);
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sc->mii_mpd_rev = MII_REV(ma->mii_id2);
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sc->mii_funcs = &igphy_funcs;
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sc->mii_pdata = mii;
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sc->mii_flags = ma->mii_flags;
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mii_lock(mii);
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PHY_RESET(sc);
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PHY_READ(sc, MII_BMSR, &sc->mii_capabilities);
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sc->mii_capabilities &= ma->mii_capmask;
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if (sc->mii_capabilities & BMSR_EXTSTAT)
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PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities);
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mii_unlock(mii);
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mii_phy_add_media(sc);
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}
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typedef struct {
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int reg;
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uint16_t val;
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} dspcode;
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static const dspcode igp1code[] = {
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{ 0x1f95, 0x0001 },
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{ 0x1f71, 0xbd21 },
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{ 0x1f79, 0x0018 },
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{ 0x1f30, 0x1600 },
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{ 0x1f31, 0x0014 },
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{ 0x1f32, 0x161c },
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{ 0x1f94, 0x0003 },
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{ 0x1f96, 0x003f },
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{ 0x2010, 0x0008 },
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{ 0, 0 },
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};
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static const dspcode igp1code_r2[] = {
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{ 0x1f73, 0x0099 },
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{ 0, 0 },
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};
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static const dspcode igp3code[] = {
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{ 0x2f5b, 0x9018},
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{ 0x2f52, 0x0000},
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{ 0x2fb1, 0x8b24},
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{ 0x2fb2, 0xf8f0},
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{ 0x2010, 0x10b0},
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{ 0x2011, 0x0000},
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{ 0x20dd, 0x249a},
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{ 0x20de, 0x00d3},
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{ 0x28b4, 0x04ce},
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{ 0x2f70, 0x29e4},
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{ 0x0000, 0x0140},
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{ 0x1f30, 0x1606},
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{ 0x1f31, 0xb814},
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{ 0x1f35, 0x002a},
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{ 0x1f3e, 0x0067},
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{ 0x1f54, 0x0065},
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{ 0x1f55, 0x002a},
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{ 0x1f56, 0x002a},
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{ 0x1f72, 0x3fb0},
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{ 0x1f76, 0xc0ff},
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{ 0x1f77, 0x1dec},
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{ 0x1f78, 0xf9ef},
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{ 0x1f79, 0x0210},
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{ 0x1895, 0x0003},
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{ 0x1796, 0x0008},
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{ 0x1798, 0xd008},
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{ 0x1898, 0xd918},
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{ 0x187a, 0x0800},
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{ 0x0019, 0x008d},
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{ 0x001b, 0x2080},
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{ 0x0014, 0x0045},
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{ 0x0000, 0x1340},
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{ 0, 0 },
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};
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/* DSP patch for igp1 and igp2 */
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static void
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igphy_load_dspcode(struct mii_softc *sc)
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{
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struct igphy_softc *igsc = (struct igphy_softc *)sc;
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const dspcode *code;
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uint16_t reg;
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int i;
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/* This workaround is only for 82541 and 82547 */
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switch (igsc->sc_mactype) {
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case WM_T_82541:
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case WM_T_82547:
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code = igp1code;
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break;
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case WM_T_82541_2:
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case WM_T_82547_2:
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code = igp1code_r2;
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break;
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default:
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return; /* byebye */
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}
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/* Delay after phy reset to enable NVM configuration to load */
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delay(20000);
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/*
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* Save off the current value of register 0x2F5B to be restored at
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* the end of this routine.
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*/
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IGPHY_READ(sc, 0x2f5b, ®);
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/* Disabled the PHY transmitter */
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IGPHY_WRITE(sc, 0x2f5b, 0x0003);
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delay(20000);
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PHY_WRITE(sc, IGPHY_PAGE_SELECT, 0x0000);
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PHY_WRITE(sc, 0x0000, 0x0140);
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delay(5000);
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for (i = 0; !((code[i].reg == 0) && (code[i].val == 0)); i++)
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IGPHY_WRITE(sc, code[i].reg, code[i].val);
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PHY_WRITE(sc, IGPHY_PAGE_SELECT, 0x0000);
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PHY_WRITE(sc, 0x0000, 0x3300);
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delay(20000);
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/* Now enable the transmitter */
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IGPHY_WRITE(sc, 0x2f5b, reg);
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}
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static void
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igphy_load_dspcode_igp3(struct mii_softc *sc)
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{
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const dspcode *code = igp3code;
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int i;
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for (i = 0; !((code[i].reg == 0) && (code[i].val == 0)); i++)
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IGPHY_WRITE(sc, code[i].reg, code[i].val);
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}
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static void
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igphy_reset(struct mii_softc *sc)
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{
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struct igphy_softc *igsc = (struct igphy_softc *)sc;
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uint16_t fused, fine, coarse;
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KASSERT(mii_locked(sc->mii_pdata));
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mii_phy_reset(sc);
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delay(150);
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switch (igsc->sc_mactype) {
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case WM_T_82541:
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case WM_T_82547:
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case WM_T_82541_2:
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case WM_T_82547_2:
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igphy_load_dspcode(sc);
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break;
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case WM_T_ICH8:
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case WM_T_ICH9:
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if ((igsc->sc_macflags & WM_F_EEPROM_INVALID) != 0)
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igphy_load_dspcode_igp3(sc);
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break;
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default: /* Not for ICH10, PCH and 8257[12] */
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break;
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}
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if (igsc->sc_mactype == WM_T_82547) {
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IGPHY_READ(sc, IGPHY_ANALOG_SPARE_FUSE_STATUS, &fused);
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if ((fused & ANALOG_SPARE_FUSE_ENABLED) == 0) {
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IGPHY_READ(sc, IGPHY_ANALOG_FUSE_STATUS, &fused);
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fine = fused & ANALOG_FUSE_FINE_MASK;
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coarse = fused & ANALOG_FUSE_COARSE_MASK;
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if (coarse > ANALOG_FUSE_COARSE_THRESH) {
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coarse -= ANALOG_FUSE_COARSE_10;
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fine -= ANALOG_FUSE_FINE_1;
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} else if (coarse == ANALOG_FUSE_COARSE_THRESH)
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fine -= ANALOG_FUSE_FINE_10;
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fused = (fused & ANALOG_FUSE_POLY_MASK) |
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(fine & ANALOG_FUSE_FINE_MASK) |
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(coarse & ANALOG_FUSE_COARSE_MASK);
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IGPHY_WRITE(sc, IGPHY_ANALOG_FUSE_CONTROL, fused);
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IGPHY_WRITE(sc, IGPHY_ANALOG_FUSE_BYPASS,
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ANALOG_FUSE_ENABLE_SW_CONTROL);
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}
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}
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PHY_WRITE(sc, IGPHY_PAGE_SELECT, 0x0000);
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}
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static int
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igphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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{
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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uint16_t reg;
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KASSERT(mii_locked(mii));
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switch (cmd) {
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case MII_POLLSTAT:
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/* If we're not polling our PHY instance, just return. */
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return 0;
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break;
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case MII_MEDIACHG:
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/*
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* If the media indicates a different PHY instance,
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* isolate ourselves.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
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PHY_READ(sc, MII_BMCR, ®);
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PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
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return 0;
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}
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/* If the interface is not up, don't do anything. */
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
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break;
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PHY_READ(sc, IGPHY_PORT_CTRL, ®);
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if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
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reg |= PSCR_AUTO_MDIX;
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reg &= ~PSCR_FORCE_MDI_MDIX;
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PHY_WRITE(sc, IGPHY_PORT_CTRL, reg);
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} else {
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reg &= ~(PSCR_AUTO_MDIX | PSCR_FORCE_MDI_MDIX);
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PHY_WRITE(sc, IGPHY_PORT_CTRL, reg);
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}
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mii_phy_setmedia(sc);
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break;
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case MII_TICK:
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/* If we're not currently selected, just return. */
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return 0;
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igphy_smartspeed_workaround(sc);
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if (mii_phy_tick(sc) == EJUSTRETURN)
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return 0;
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break;
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case MII_DOWN:
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mii_phy_down(sc);
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return 0;
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}
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/* Update the media status. */
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mii_phy_status(sc);
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/* Callback if something changed. */
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mii_phy_update(sc, cmd);
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return 0;
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}
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static void
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igphy_status(struct mii_softc *sc)
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{
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struct mii_data *mii = sc->mii_pdata;
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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uint16_t bmcr, pssr, gtsr, bmsr;
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KASSERT(mii_locked(mii));
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mii->mii_media_status = IFM_AVALID;
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mii->mii_media_active = IFM_ETHER;
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PHY_READ(sc, IGPHY_PORT_STATUS, &pssr);
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if (pssr & IGPHY_PSSR_LINK_UP)
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mii->mii_media_status |= IFM_ACTIVE;
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PHY_READ(sc, MII_BMCR, &bmcr);
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if (bmcr & BMCR_ISO) {
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mii->mii_media_active |= IFM_NONE;
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return;
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}
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if (bmcr & BMCR_LOOP)
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mii->mii_media_active |= IFM_LOOP;
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PHY_READ(sc, MII_BMSR, &bmsr);
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PHY_READ(sc, MII_BMSR, &bmsr);
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/* XXX can't check if the info is valid, no 'negotiation done' bit? */
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if (bmcr & BMCR_AUTOEN) {
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if ((bmsr & BMSR_ACOMP) == 0) {
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mii->mii_media_active |= IFM_NONE;
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return;
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}
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switch (pssr & IGPHY_PSSR_SPEED_MASK) {
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case IGPHY_PSSR_SPEED_1000MBPS:
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mii->mii_media_active |= IFM_1000_T;
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PHY_READ(sc, MII_100T2SR, >sr);
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if (gtsr & GTSR_MS_RES)
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mii->mii_media_active |= IFM_ETH_MASTER;
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break;
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case IGPHY_PSSR_SPEED_100MBPS:
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mii->mii_media_active |= IFM_100_TX;
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break;
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case IGPHY_PSSR_SPEED_10MBPS:
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mii->mii_media_active |= IFM_10_T;
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break;
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default:
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mii->mii_media_active |= IFM_NONE;
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mii->mii_media_status = 0;
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return;
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}
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if (pssr & IGPHY_PSSR_FULL_DUPLEX)
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mii->mii_media_active |=
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IFM_FDX | mii_phy_flowstatus(sc);
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else
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mii->mii_media_active |= IFM_HDX;
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} else
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mii->mii_media_active = ife->ifm_media;
|
|
}
|
|
|
|
static void
|
|
igphy_smartspeed_workaround(struct mii_softc *sc)
|
|
{
|
|
struct igphy_softc *igsc = (struct igphy_softc *)sc;
|
|
uint16_t reg, gtsr, gtcr;
|
|
|
|
/* This workaround is only for 82541 and 82547 */
|
|
switch (igsc->sc_mactype) {
|
|
case WM_T_82541:
|
|
case WM_T_82541_2:
|
|
case WM_T_82547:
|
|
case WM_T_82547_2:
|
|
break;
|
|
default:
|
|
/* byebye */
|
|
return;
|
|
}
|
|
|
|
PHY_READ(sc, MII_BMCR, ®);
|
|
if ((reg & BMCR_AUTOEN) == 0)
|
|
return;
|
|
|
|
/* XXX Assume 1000TX-FDX is advertized if doing autonegotiation. */
|
|
|
|
PHY_READ(sc, MII_BMSR, ®);
|
|
PHY_READ(sc, MII_BMSR, ®);
|
|
if ((reg & BMSR_LINK) == 0) {
|
|
switch (igsc->sc_smartspeed) {
|
|
case 0:
|
|
PHY_READ(sc, MII_100T2SR, >sr);
|
|
if (!(gtsr & GTSR_MAN_MS_FLT))
|
|
break;
|
|
PHY_READ(sc, MII_100T2SR, >sr);
|
|
if (gtsr & GTSR_MAN_MS_FLT) {
|
|
PHY_READ(sc, MII_100T2CR, >cr);
|
|
if (gtcr & GTCR_MAN_MS) {
|
|
gtcr &= ~GTCR_MAN_MS;
|
|
PHY_WRITE(sc, MII_100T2CR, gtcr);
|
|
}
|
|
mii_phy_auto(sc);
|
|
}
|
|
break;
|
|
case IGPHY_TICK_DOWNSHIFT:
|
|
PHY_READ(sc, MII_100T2CR, >cr);
|
|
gtcr |= GTCR_MAN_MS;
|
|
PHY_WRITE(sc, MII_100T2CR, gtcr);
|
|
mii_phy_auto(sc);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
if (igsc->sc_smartspeed++ == IGPHY_TICK_MAX)
|
|
igsc->sc_smartspeed = 0;
|
|
} else
|
|
igsc->sc_smartspeed = 0;
|
|
}
|