162 lines
6.6 KiB
C
162 lines
6.6 KiB
C
/* $NetBSD: iommureg.h,v 1.5 2000/06/12 23:19:05 eeh Exp $ */
|
|
|
|
/*
|
|
* Copyright (c) 1992, 1993
|
|
* The Regents of the University of California. All rights reserved.
|
|
*
|
|
* This software was developed by the Computer Systems Engineering group
|
|
* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
|
|
* contributed to Berkeley.
|
|
*
|
|
* All advertising materials mentioning features or use of this software
|
|
* must display the following acknowledgement:
|
|
* This product includes software developed by the University of
|
|
* California, Lawrence Berkeley Laboratory.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions
|
|
* are met:
|
|
* 1. Redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer.
|
|
* 2. Redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution.
|
|
* 3. All advertising materials mentioning features or use of this software
|
|
* must display the following acknowledgement:
|
|
* This product includes software developed by the University of
|
|
* California, Berkeley and its contributors.
|
|
* 4. Neither the name of the University nor the names of its contributors
|
|
* may be used to endorse or promote products derived from this software
|
|
* without specific prior written permission.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
|
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
|
* SUCH DAMAGE.
|
|
*
|
|
* @(#)sbusreg.h 8.1 (Berkeley) 6/11/93
|
|
*/
|
|
|
|
#ifndef _SPARC64_DEV_IOMMUREG_H_
|
|
#define _SPARC64_DEV_IOMMUREG_H_
|
|
|
|
/*
|
|
* UltraSPARC IOMMU registers, common to both the sbus and PCI
|
|
* controllers.
|
|
*/
|
|
|
|
/* iommmu registers */
|
|
struct iommureg {
|
|
u_int64_t iommu_cr; /* IOMMU control register */
|
|
u_int64_t iommu_tsb; /* IOMMU TSB base register */
|
|
u_int64_t iommu_flush; /* IOMMU flush register */
|
|
};
|
|
|
|
/* streaming buffer registers */
|
|
struct iommu_strbuf {
|
|
u_int64_t strbuf_ctl; /* streaming buffer control reg */
|
|
u_int64_t strbuf_pgflush; /* streaming buffer page flush */
|
|
u_int64_t strbuf_flushsync;/* streaming buffer flush sync */
|
|
};
|
|
|
|
/* streaming buffer control register */
|
|
#define STRBUF_EN 0x000000000000000001LL
|
|
#define STRBUF_D 0x000000000000000002LL
|
|
|
|
/* control register bits */
|
|
#define IOMMUCR_TSB1K 0x000000000000000000LL /* Nummber of entries in IOTSB */
|
|
#define IOMMUCR_TSB2K 0x000000000000010000LL
|
|
#define IOMMUCR_TSB4K 0x000000000000020000LL
|
|
#define IOMMUCR_TSB8K 0x000000000000030000LL
|
|
#define IOMMUCR_TSB16K 0x000000000000040000LL
|
|
#define IOMMUCR_TSB32K 0x000000000000050000LL
|
|
#define IOMMUCR_TSB64K 0x000000000000060000LL
|
|
#define IOMMUCR_TSB128K 0x000000000000070000LL
|
|
#define IOMMUCR_TSBMASK 0xfffffffffffff8ffffLL /* Mask for above */
|
|
#define IOMMUCR_8KPG 0x000000000000000000LL /* 8K iommu page size */
|
|
#define IOMMUCR_64KPG 0x000000000000000004LL /* 64K iommu page size */
|
|
#define IOMMUCR_DE 0x000000000000000002LL /* Diag enable */
|
|
#define IOMMUCR_EN 0x000000000000000001LL /* Enable IOMMU */
|
|
|
|
/*
|
|
* IOMMU stuff
|
|
*/
|
|
#define IOTTE_V 0x8000000000000000LL /* Entry valid */
|
|
#define IOTTE_64K 0x2000000000000000LL /* 8K or 64K page? */
|
|
#define IOTTE_8K 0x0000000000000000LL
|
|
#define IOTTE_STREAM 0x1000000000000000LL /* Is page streamable? */
|
|
#define IOTTE_LOCAL 0x0800000000000000LL /* Accesses to same bus segment? */
|
|
#define IOTTE_PAMASK 0x000001ffffffe000LL /* Let's assume this is correct */
|
|
#define IOTTE_C 0x0000000000000010LL /* Accesses to cacheable space */
|
|
#define IOTTE_W 0x0000000000000002LL /* Writeable */
|
|
|
|
/*
|
|
* On sun4u each bus controller has a separate IOMMU. The IOMMU has
|
|
* a TSB which must be page aligned and physically contiguous. Mappings
|
|
* can be of 8K IOMMU pages or 64K IOMMU pages. We use 8K for compatibility
|
|
* with the CPU's MMU.
|
|
*
|
|
* IOMMU TSBs using 8K pages can map the following size segments:
|
|
*
|
|
* VA size VA base TSB size tsbsize
|
|
* -------- -------- --------- -------
|
|
* 8MB ff800000 8K 0
|
|
* 16MB ff000000 16K 1
|
|
* 32MB fe000000 32K 2
|
|
* 64MB fc000000 64K 3
|
|
* 128MB f8000000 128K 4
|
|
* 256MB f0000000 256K 5
|
|
* 512MB e0000000 512K 6
|
|
* 1GB c0000000 1MB 7
|
|
*
|
|
* The UltraSPARC IIi IOMMU only seems to support 1GB VA size.
|
|
*/
|
|
|
|
|
|
#define IOTSB_VEND (0xffffffffffffffffLL<<PGSHIFT)
|
|
#define IOTSB_VSTART(sz) (u_int)(IOTSB_VEND << ((sz)+10))
|
|
|
|
#define MAKEIOTTE(pa,w,c,s) (((pa)&IOTTE_PAMASK)|((w)?IOTTE_W:0)|((c)?IOTTE_C:0)|((s)?IOTTE_STREAM:0)|(IOTTE_V|IOTTE_8K))
|
|
#if 0
|
|
/* This version generates a pointer to a int64_t */
|
|
#define IOTSBSLOT(va,sz) ((((((vaddr_t)(va))-((vaddr_t)IOTSB_VSTART(sz))))>>(PGSHIFT-3))&(~7))
|
|
#else
|
|
/* Here we just try to create an array index */
|
|
#define IOTSBSLOT(va,sz) ((u_int)((((((vaddr_t)(va))-((vaddr_t)IOTSB_VSTART(sz))))>>(PGSHIFT))))
|
|
#endif
|
|
|
|
/*
|
|
* interrupt map stuff. this belongs elsewhere.
|
|
*/
|
|
|
|
#define INTMAP_V 0x080000000LL /* Interrupt valid (enabled) */
|
|
#define INTMAP_TID 0x07c000000LL /* UPA target ID mask */
|
|
#define INTMAP_IGN 0x0000007c0LL /* Interrupt group no (sbus only). */
|
|
#define INTMAP_INO 0x00000003fLL /* Interrupt number */
|
|
#define INTMAP_INR (INTMAP_IGN|INTMAP_INO)
|
|
#define INTMAP_SBUSSLOT 0x000000018LL /* SBUS slot # */
|
|
#define INTMAP_PCIBUS 0x000000010LL /* PCI bus number (A or B) */
|
|
#define INTMAP_PCISLOT 0x00000000cLL /* PCI slot # */
|
|
#define INTMAP_PCIINT 0x000000003LL /* PCI interrupt #A,#B,#C,#D */
|
|
#define INTMAP_OBIO 0x000000020LL /* Onboard device */
|
|
#define INTMAP_LSHIFT 11 /* Encode level in vector */
|
|
#define INTLEVENCODE(x) (((x)&0x0f)<<INTMAP_LSHIFT)
|
|
#define INTLEV(x) (((x)>>INTMAP_LSHIFT)&0x0f)
|
|
#define INTVEC(x) ((x)&INTMAP_INR)
|
|
#define INTSLOT(x) (((x)>>3)&0x7)
|
|
#define INTPRI(x) ((x)&0x7)
|
|
#define INTINO(x) ((x)&INTMAP_INO)
|
|
|
|
#define INTPCI_MAXOBINO 0x16 /* maximum OBIO INO value for PCI */
|
|
#define INTPCIOBINOX(x) ((x)&0x1f) /* OBIO ino index (for PCI machines) */
|
|
#define INTPCIINOX(x) (((x)&0x1c)>>2) /* PCI ino index */
|
|
|
|
#endif /* _SPARC64_DEV_IOMMUREG_H_ */
|