185 lines
6.7 KiB
C
185 lines
6.7 KiB
C
/* $NetBSD: vme_pccreg.h,v 1.5 2000/11/24 09:27:42 scw Exp $ */
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/*-
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* Copyright (c) 1996 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MVME68K_VME_PCCREG_H
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#define _MVME68K_VME_PCCREG_H
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/*
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* Register map of the Type 1 VMEchip found on the MVME-147
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* Peripheral Channel Controller.
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*/
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/*
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* Local control registers...
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*/
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#define VME1REG_SCON 0x01
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#define VME1_SCON_SWITCH 0x01 /* SCON jumper is set */
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#define VME1_SCON_SRESET 0x02 /* assert SRESET on bus */
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#define VME1_SCON_SYSFAIL 0x04 /* assert SYSFAIL on bus */
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#define VME1_SCON_ROBIN 0x08 /* round robin bus requests */
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#define VME1REG_REQCONF 0x03
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#define VME1_REQ_IPLMASK 0x03 /* interrupt level for requester */
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#define VME1_REQ_RNEVER 0x08
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#define VME1_REQ_RWD 0x10
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#define VME1_REQ_DHB 0x40
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#define VME1_REQ_DWB 0x80
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#define VME1REG_MASCONF 0x05
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#define VME1_MAS_D16 0x01 /* force d8/16 accesses only */
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#define VME1_MAS_MASA24 0x02 /* send address mod for A24 access */
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#define VME1_MAS_MASA16 0x04 /* send address mod for A16 access */
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#define VME1_MAS_MASUAT 0x08 /* handle unaligned VME cycles */
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#define VME1_MAS_CFILL 0x10 /* DO NOT USE */
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#define VME1_MAS_MASWP 0x20 /* VME fast mode (DO NOT USE) */
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#define VME1REG_SLCONF 0x07
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#define VME1_SLAVE_SLVD16 0x01 /* DO NOT USE */
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#define VME1_SLAVE_SLVWP 0x20 /* DO NOT USE */
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#define VME1_SLAVE_SLVEN 0x80 /* allow access to onboard DRAM */
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#define VME1REG_TIMERCONF 0x09
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#define VME1_TIMER_LOCAL_MASK 0x03
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#define VME1_TIMER_LOCAL_T0 0x00 /* local timeout 102 microsec */
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#define VME1_TIMER_LOCAL_T1 0x01 /* local timeout 205 microsec */
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#define VME1_TIMER_LOCAL_T2 0x02 /* local timeout 410 microsec */
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#define VME1_TIMER_LOCAL_T3 0x03 /* local timeout disabled */
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#define VME1_TIMER_VMEACC_MASK 0x0c
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#define VME1_TIMER_VMEACC_T0 0x00 /* VME access timeout 102 microsec */
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#define VME1_TIMER_VMEACC_T1 0x04 /* VME access timeout 1.6 millisec */
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#define VME1_TIMER_VMEACC_T2 0x08 /* VME access timeout 51 millisec */
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#define VME1_TIMER_VMEACC_T3 0x0c /* VME access timeout disabled */
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#define VME1_TIMER_VMEGLO_MASK 0x30
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#define VME1_TIMER_VMEGLO_T0 0x00 /* VME glob timeout 102 microsec */
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#define VME1_TIMER_VMEGLO_T1 0x10 /* VME glob timeout 205 microsec */
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#define VME1_TIMER_VMEGLO_T2 0x20 /* VME glob timeout 410 microsec */
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#define VME1_TIMER_VMEGLO_T3 0x30 /* VME glob timeout disabled */
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#define VME1_TIMER_ARBTO 0x40 /* enable VME arbitration timer */
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#define VME1REG_SLADDRMOD 0x0b
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#define VME1_SLMOD_DATA 0x01
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#define VME1_SLMOD_PRGRM 0x02
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#define VME1_SLMOD_BLOCK 0x04
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#define VME1_SLMOD_SHORT 0x08
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#define VME1_SLMOD_STND 0x10
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#define VME1_SLMOD_EXTED 0x20
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#define VME1_SLMOD_USER 0x40
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#define VME1_SLMOD_SUPER 0x80
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#define VME1REG_MSADDRMOD 0x0d
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#define VME1_MSMOD_AM_MASK 0x3f
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#define VME1_MSMOD_AMSEL 0x80
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#define VME1REG_IRQEN 0x0f
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#define VME1_IRQ_VME(x) (1 << (x))
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#define VME1REG_UIREQEN 0x11
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#define VME1REG_UIRQ 0x13
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#define VME1REG_IRQ 0x15
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#define VME1REG_VMEID 0x17
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#define VME1REG_BUSERR 0x19
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#define VME1REG_GCSR 0x1b
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/*
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* Global Status and Control registers.
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*/
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#define VME1REG_GCSR_GR0 0x21
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#define VME1REG_GCSR_GR1 0x23
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#define VME1REG_GCSR_BOARDID 0x25
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#define VME1REG_GCSR_GPR0 0x27
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#define VME1REG_GCSR_GPR1 0x29
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#define VME1REG_GCSR_GPR2 0x2b
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#define VME1REG_GCSR_GPR3 0x2d
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#define VME1REG_GCSR_GPR4 0x2f
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/*
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* Length of the VME chip's register mapping
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*/
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#define VME1REG_SIZE 0x30
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/*
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* Convenience macros for reading and writing the registers
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*/
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#define vme1_reg_read(sc,r) \
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bus_space_read_1((sc)->sc_mvmebus.sc_bust, (sc)->sc_bush, (r))
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#define vme1_reg_write(sc,r,v) \
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bus_space_write_1((sc)->sc_mvmebus.sc_bust, (sc)->sc_bush, (r), (v))
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/*
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* The Type 1 VMEchip decoder maps VME address space to system addresses
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* like this:
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*
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* A24D32: 0x00000000 - 0x00ffffff
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* A32D32: 0x01000000 - 0xefffffff
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* A24D16: 0xf0000000 - 0xf0ffffff
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* A32D16: 0xf1000000 - 0xff7fffff
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* A16D16: 0xffff0000 - 0xffffffff
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*
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* Note that the first A24D32 range is overlayed with onboard RAM. Thus
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* an 8Mb board will only allow A24D32:0x00800000 - 0x00ffffff. When
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* onboard RAM is >= 16Mb, the A24D32 range is unavailable and the RAM
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* starts encroaching on the A32D32 range.
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*/
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#define VME1_A24D32_LOC_START (0x00000000u)
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#define VME1_A24D32_START (0x00000000u)
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#define VME1_A24D32_END (0x00ffffffu)
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#define VME1_A32D32_LOC_START (0x00000000u)
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#define VME1_A32D32_START (0x01000000u)
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#define VME1_A32D32_END (0xefffffffu)
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#define VME1_A24D16_LOC_START (0xf0000000u)
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#define VME1_A24D16_START (0x00000000u)
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#define VME1_A24D16_END (0x00ffffffu)
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#define VME1_A32D16_LOC_START (0x00000000u)
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#define VME1_A32D16_START (0xf1000000u)
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#define VME1_A32D16_END (0xff7fffffu)
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#define VME1_A16D16_LOC_START (0xffff0000u)
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#define VME1_A16D16_START (0x00000000u)
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#define VME1_A16D16_END (0x0000ffffu)
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#define VME1_A32_MASK (0xffffffffu)
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#define VME1_A24_MASK (0x00ffffffu)
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#define VME1_A16_MASK (0x0000ffffu)
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#endif /* _MVME68K_VME_PCCREG_H */
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