309 lines
16 KiB
C
309 lines
16 KiB
C
/* $NetBSD: trmreg.h,v 1.1 2001/11/03 17:01:18 tsutsui Exp $ */
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/*
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* Device Driver for Tekram DC395U/UW/F, DC315/U
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* PCI SCSI Bus Master Host Adapter
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* (SCSI chip set used Tekram ASIC TRM-S1040)
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*
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* Copyright (c) 2001 Rui-Xiang Guo
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Ported from
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* dc395x_trm.h
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*
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* Written for NetBSD 1.4.x by
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* Erich Chen (erich@tekram.com.tw)
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*
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* Provided by
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* (C)Copyright 1995-1999 Tekram Technology Co., Ltd. All rights reserved.
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*/
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/*
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**********************************************************************
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*
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* The SCSI register offset for TRM_S1040
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*
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**********************************************************************
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*/
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#define TRM_SCSI_STATUS 0x80 /* SCSI Status (R) */
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#define COMMANDPHASEDONE 0x2000 /* SCSI command phase done */
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#define SCSIXFERDONE 0x0800 /* SCSI transfer done */
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#define SCSIXFERCNT_2_ZERO 0x0100 /* SCSI transfer count to zero */
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#define SCSIINTERRUPT 0x0080 /* SCSI interrupt pending */
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#define COMMANDABORT 0x0040 /* SCSI command abort */
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#define SEQUENCERACTIVE 0x0020 /* SCSI sequencer active */
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#define PHASEMISMATCH 0x0010 /* SCSI phase mismatch */
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#define PARITYERROR 0x0008 /* SCSI parity error */
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#define PHASEMASK 0x0007 /* Phase MSG/CD/IO */
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#define PH_DATA_OUT 0x00 /* Data out phase */
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#define PH_DATA_IN 0x01 /* Data in phase */
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#define PH_COMMAND 0x02 /* Command phase */
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#define PH_STATUS 0x03 /* Status phase */
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#define PH_BUS_FREE 0x05 /* Invalid phase as bus free */
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#define PH_MSG_OUT 0x06 /* Message out phase */
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#define PH_MSG_IN 0x07 /* Message in phase */
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#define TRM_SCSI_CONTROL 0x80 /* SCSI Control (W) */
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#define DO_CLRATN 0x0400 /* Clear ATN */
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#define DO_SETATN 0x0200 /* Set ATN */
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#define DO_CMDABORT 0x0100 /* Abort SCSI command */
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#define DO_RSTMODULE 0x0010 /* Reset SCSI chip */
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#define DO_RSTSCSI 0x0008 /* Reset SCSI bus */
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#define DO_CLRFIFO 0x0004 /* Clear SCSI transfer FIFO */
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#define DO_DATALATCH 0x0002 /* Enable SCSI bus data latch */
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#define DO_HWRESELECT 0x0001 /* Enable hardware reselection */
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#define TRM_SCSI_FIFOCNT 0x82 /* SCSI FIFO Counter (R) */
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#define SCSI_FIFOCNT_MASK 0x1F /* 5 bits SCSI FIFO counter */
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#define SCSI_FIFO_EMPTY 0x40 /* SCSI FIFO Empty */
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#define TRM_SCSI_SIGNAL 0x83 /* SCSI low level signal (R/W) */
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#define TRM_SCSI_INTSTATUS 0x84 /* SCSI Interrupt Status (R) */
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#define INT_SCAM 0x80 /* SCAM selection interrupt */
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#define INT_SELECT 0x40 /* Selection interrupt */
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#define INT_SELTIMEOUT 0x20 /* Selection timeout interrupt */
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#define INT_DISCONNECT 0x10 /* Bus disconnected interrupt */
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#define INT_RESELECTED 0x08 /* Reselected interrupt */
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#define INT_SCSIRESET 0x04 /* SCSI reset detected interrupt */
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#define INT_BUSSERVICE 0x02 /* Bus service interrupt */
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#define INT_CMDDONE 0x01 /* SCSI command done interrupt */
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#define TRM_SCSI_OFFSET 0x84 /* SCSI Offset Count (W) */
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/*
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* Bit Name Definition
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* 07-05 0 RSVD Reversed. Always 0.
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* 04 0 OFFSET4 Reversed for LVDS. Always 0.
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* 03-00 0 OFFSET[03:00] Offset number from 0 to 15
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*/
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#define TRM_SCSI_SYNC 0x85 /* SCSI Sync Control (R/W) */
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#define LVDS_SYNC 0x20 /* Enable LVDS sync */
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#define WIDE_SYNC 0x10 /* Enable WIDE sync */
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#define ALT_SYNC 0x08 /* Enable Fast-20 alternate sync */
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/*
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* SYNCM 7 6 5 4 3 2 1 0
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* Name RSVD RSVD LVDS WIDE ALTPERD PERIOD2 PERIOD1 PERIOD0
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* Default 0 0 0 0 0 0 0 0
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*
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* Bit Name Definition
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* 07-06 0 RSVD Reversed. Always read 0
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* 05 0 LVDS Reversed. Always read 0
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* 04 0 WIDE/WSCSI Enable wide (16-bits) SCSI transfer.
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* 03 0 ALTPERD/ALTPD Alternate (Sync./Period) mode.
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*
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* @@ When this bit is set,
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* the synchronous period bits 2:0
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* in the Synchronous Mode register
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* are used to transfer data
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* at the Fast-20 rate.
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* @@ When this bit is reset,
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* the synchronous period bits 2:0
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* in the Synchronous Mode Register
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* are used to transfer data
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* at the Fast-40 rate.
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*
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* 02-00 0 PERIOD[2:0]/SXPD[02:00] Synchronous SCSI Transfer Rate.
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* These 3 bits specify
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* the Synchronous SCSI Transfer Rate
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* for Fast-20 and Fast-10.
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* These bits are also reset
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* by a SCSI Bus reset.
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*
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* For Fast-10 bit ALTPD = 0 and LVDS = 0
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* and bit2,bit1,bit0 is defined as follows :
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*
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* 000 100ns, 10.0 Mbytes/s
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* 001 150ns, 6.6 Mbytes/s
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* 010 200ns, 5.0 Mbytes/s
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* 011 250ns, 4.0 Mbytes/s
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* 100 300ns, 3.3 Mbytes/s
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* 101 350ns, 2.8 Mbytes/s
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* 110 400ns, 2.5 Mbytes/s
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* 111 450ns, 2.2 Mbytes/s
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*
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* For Fast-20 bit ALTPD = 1 and LVDS = 0
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* and bit2,bit1,bit0 is defined as follows :
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*
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* 000 50ns, 20.0 Mbytes/s
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* 001 75ns, 13.3 Mbytes/s
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* 010 100ns, 10.0 Mbytes/s
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* 011 125ns, 8.0 Mbytes/s
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* 100 150ns, 6.6 Mbytes/s
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* 101 175ns, 5.7 Mbytes/s
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* 110 200ns, 5.0 Mbytes/s
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* 111 250ns, 4.0 Mbytes/s
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*
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* For Fast-40 bit ALTPD = 0 and LVDS = 1
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* and bit2,bit1,bit0 is defined as follows :
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*
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* 000 25ns, 40.0 Mbytes/s
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* 001 50ns, 20.0 Mbytes/s
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* 010 75ns, 13.3 Mbytes/s
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* 011 100ns, 10.0 Mbytes/s
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* 100 125ns, 8.0 Mbytes/s
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* 101 150ns, 6.6 Mbytes/s
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* 110 175ns, 5.7 Mbytes/s
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* 111 200ns, 5.0 Mbytes/s
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*/
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#define TRM_SCSI_TARGETID 0x86 /* SCSI Target ID (R/W) */
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#define TRM_SCSI_IDMSG 0x87 /* SCSI Identify Message (R) */
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#define TRM_SCSI_HOSTID 0x87 /* SCSI Host ID (W) */
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#define TRM_SCSI_XCNT 0x88 /* SCSI Transfer Counter (R/W) */
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#define SCSI_XCNT_MASK 0x00FFFFFF /* 24 bits SCSI transfer counter */
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#define TRM_SCSI_INTEN 0x8C /* SCSI Interrupt Enable (R/W) */
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#define EN_SCAM 0x80 /* Enable SCAM selection intr */
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#define EN_SELECT 0x40 /* Enable selection intr */
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#define EN_SELTIMEOUT 0x20 /* Enable selection timeout intr */
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#define EN_DISCONNECT 0x10 /* Enable bus disconnected intr */
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#define EN_RESELECTED 0x08 /* Enable reselected intr */
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#define EN_SCSIRESET 0x04 /* Enable SCSI reset detected intr */
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#define EN_BUSSERVICE 0x02 /* Enable bus service intr */
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#define EN_CMDDONE 0x01 /* Enable SCSI command done intr */
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#define TRM_SCSI_CONFIG0 0x8D /* SCSI Configuration 0 (R/W) */
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#define PHASELATCH 0x40 /* Enable phase latch */
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#define INITIATOR 0x20 /* Enable initiator mode */
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#define PARITYCHECK 0x10 /* Enable parity check */
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#define BLOCKRST 0x01 /* Disable SCSI reset */
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#define TRM_SCSI_CONFIG1 0x8E /* SCSI Configuration 1 (R/W) */
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#define ACTIVE_NEGPLUS 0x10 /* Enhance active negation */
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#define FILTER_DISABLE 0x08 /* Disable SCSI data filter */
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#define ACTIVE_NEG 0x02 /* Enable active negation */
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#define TRM_SCSI_COMMAND 0x90 /* SCSI Command (R/W) */
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#define SCMD_COMP 0x12 /* Command complete */
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#define SCMD_SEL_ATN 0x60 /* Selection with ATN */
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#define SCMD_SEL_ATN3 0x64 /* Selection with ATN3 */
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#define SCMD_SEL_ATNSTOP 0xB8 /* Selection with ATN and Stop */
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#define SCMD_FIFO_OUT 0xC0 /* SCSI FIFO transfer out */
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#define SCMD_DMA_OUT 0xC1 /* SCSI DMA transfer out */
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#define SCMD_FIFO_IN 0xC2 /* SCSI FIFO transfer in */
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#define SCMD_DMA_IN 0xC3 /* SCSI DMA transfer in */
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#define SCMD_MSGACCEPT 0xD8 /* Message accept */
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/*
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* Code Command Description
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*
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* 02 Enable reselection with FIFO
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* 40 Select without ATN with FIFO
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* 60 Select with ATN with FIFO
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* 64 Select with ATN3 with FIFO
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* A0 Select with ATN and stop with FIFO
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* C0 Transfer information out with FIFO
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* C1 Transfer information out with DMA
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* C2 Transfer information in with FIFO
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* C3 Transfer information in with DMA
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* 12 Initiator command complete with FIFO
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* 50 Initiator transfer information out sequence without ATN with FIFO
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* 70 Initiator transfer information out sequence with ATN with FIFO
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* 74 Initiator transfer information out sequence with ATN3 with FIFO
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* 52 Initiator transfer information in sequence without ATN with FIFO
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* 72 Initiator transfer information in sequence with ATN with FIFO
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* 76 Initiator transfer information in sequence with ATN3 with FIFO
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* 90 Initiator transfer information out command complete with FIFO
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* 92 Initiator transfer information in command complete with FIFO
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* D2 Enable selection
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* 08 Reselection
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* 48 Disconnect command with FIFO
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* 88 Terminate command with FIFO
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* C8 Target command complete with FIFO
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* 18 SCAM Arbitration/ Selection
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* 5A Enable reselection
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* 98 Select without ATN with FIFO
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* B8 Select with ATN with FIFO
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* D8 Message Accepted
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* 58 NOP
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*/
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#define TRM_SCSI_TIMEOUT 0x91 /* SCSI Time Out Value (R/W) */
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#define SEL_TIMEOUT 153 /* 250ms selection timeout (@ 40 MHz) */
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#define TRM_SCSI_FIFO 0x98 /* SCSI FIFO (R/W) */
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#define TRM_SCSI_TCR0 0x9C /* SCSI Target Control 0 (R/W) */
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#define TCR0_WIDE_NEGO_DONE 0x8000 /* Wide nego done */
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#define TCR0_SYNC_NEGO_DONE 0x4000 /* Sync nego done */
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#define TCR0_ENABLE_LVDS 0x2000 /* Enable LVDS sync */
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#define TCR0_ENABLE_WIDE 0x1000 /* Enable WIDE sync */
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#define TCR0_ENABLE_ALT 0x0800 /* Enable alternate sync */
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#define TCR0_PERIOD_MASK 0x0700 /* Transfer rate */
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#define TCR0_DO_WIDE_NEGO 0x0080 /* Do wide NEGO */
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#define TCR0_DO_SYNC_NEGO 0x0040 /* Do sync NEGO */
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#define TCR0_DISCONNECT_EN 0x0020 /* Disconnection enable */
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#define TCR0_OFFSET_MASK 0x001F /* Offset number */
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#define TRM_SCSI_TCR1 0x9E /* SCSI Target Control 1 (R/W) */
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#define MAXTAG_MASK 0x7F00 /* Maximum tags (127) */
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#define NON_TAG_BUSY 0x0080 /* Non tag command active */
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#define ACTTAG_MASK 0x007F /* Active tags */
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/*
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**********************************************************************
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*
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* The DMA register offset for TRM_S1040
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*
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**********************************************************************
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*/
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#define TRM_DMA_COMMAND 0xA0 /* DMA Command (R/W) */
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#define SGXFER 0x02 /* Scatter/Gather transfer */
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#define XFERDATAIN 0x01 /* Transfer data in */
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#define XFERDATAOUT 0x00 /* Transfer data out */
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#define TRM_DMA_CONTROL 0xA1 /* DMA Control (W) */
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#define STOPDMAXFER 0x08 /* Stop DMA transfer */
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#define ABORTXFER 0x04 /* Abort DMA transfer */
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#define CLRXFIFO 0x02 /* Clear DMA transfer FIFO */
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#define STARTDMAXFER 0x01 /* Start DMA transfer */
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#define TRM_DMA_FIFOCNT 0xA1 /* DMA FIFO Counter (R) */
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#define DMA_FIFOCNT_MASK 0xFF /* Data FIFO Count */
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#define TRM_DMA_FIFOSTATUS 0xA2 /* DMA FIFO Status (R) */
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#define DMA_FIFO_EMPTY 0x80 /* DMA FIFO Empty */
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#define DMA_FIFO_FULL 0x01 /* DMA FIFO Full */
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#define TRM_DMA_STATUS 0xA3 /* DMA Interrupt Status (R/W) */
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#define XFERPENDING 0x80 /* Transfer pending */
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#define DMAXFERCOMP 0x02 /* Bus Master XFER Complete status */
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#define SCSICOMP 0x01 /* SCSI complete interrupt */
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#define TRM_DMA_INTEN 0xA4 /* DMA Interrupt Enable (R/W) */
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#define EN_SCSIINTR 0x01 /* Enable SCSI complete interrupt */
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#define TRM_DMA_CONFIG 0xA6 /* DMA Configuration (R/W) */
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#define DMA_ENHANCE 0x8000 /* Enable DMA enhance feature */
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#define TRM_DMA_XCNT 0xA8 /* DMA Transfer Counter (R/W) */
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#define TRM_DMA_CXCNT 0xAC /* DMA Current Transfer Counter (R) */
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#define TRM_DMA_XLOWADDR 0xB0 /* DMA Xfer Physical Low Addr (R/W) */
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#define TRM_DMA_XHIGHADDR 0xB4 /* DMA Xfer Physical High Addr (R/W) */
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/*
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**********************************************************************
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*
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* The general register offset for TRM_S1040
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*
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**********************************************************************
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*/
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#define TRM_GEN_CONTROL 0xD4 /* Global Control (R/W) */
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#define EN_LED 0x80 /* Enable Control onboard LED */
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#define EN_EEPROM 0x10 /* Enable EEPROM programming */
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#define AUTOTERM 0x04 /* Enable Auto SCSI terminator */
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#define LOW8TERM 0x02 /* Enable Lower 8 bit SCSI terminator */
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#define UP8TERM 0x01 /* Enable Upper 8 bit SCSI terminator */
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#define TRM_GEN_STATUS 0xD5 /* Global Status (R) */
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#define GTIMEOUT 0x80 /* Global timer reach 0 */
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#define CON5068 0x10 /* External 50/68 pin connected */
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#define CON68 0x08 /* Internal 68 pin connected */
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#define CON50 0x04 /* Internal 50 pin connected */
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#define WIDESCSI 0x02 /* Wide SCSI card */
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#define TRM_GEN_NVRAM 0xD6 /* Serial NON-VOLATILE RAM port (R/W) */
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#define NVR_BITOUT 0x08 /* Serial data out */
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#define NVR_BITIN 0x04 /* Serial data in */
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#define NVR_CLOCK 0x02 /* Serial clock */
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#define NVR_SELECT 0x01 /* Serial select */
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#define TRM_GEN_EDATA 0xD7 /* Parallel EEPROM data port (R/W) */
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#define TRM_GEN_EADDRESS 0xD8 /* Parallel EEPROM address (R/W) */
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#define TRM_GEN_TIMER 0xDB /* Global timer (R/W) */
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