231 lines
6.0 KiB
C
231 lines
6.0 KiB
C
/* $NetBSD: macepci.c,v 1.3 2000/06/14 22:32:20 soren Exp $ */
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/*
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* Copyright (c) 2000 Soren S. Jorvang
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the
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* NetBSD Project. See http://www.netbsd.org/ for
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* information about NetBSD.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/device.h>
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#include <sys/systm.h>
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#include <machine/cpu.h>
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#include <machine/locore.h>
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#include <machine/autoconf.h>
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#include <machine/bus.h>
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#include <dev/pci/pcivar.h>
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#include <sgimips/dev/macereg.h>
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#include <sgimips/dev/macevar.h>
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#include <sgimips/pci/macepcireg.h>
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#include "pci.h"
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struct macepci_softc {
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struct device sc_dev;
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struct sgimips_pci_chipset sc_pc;
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};
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static int macepci_match(struct device *, struct cfdata *, void *);
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static void macepci_attach(struct device *, struct device *, void *);
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static int macepci_print(void *, const char *);
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pcireg_t macepci_conf_read(pci_chipset_tag_t, pcitag_t, int);
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void macepci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t);
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int macepci_intr(void *);
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struct cfattach macepci_ca = {
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sizeof(struct macepci_softc), macepci_match, macepci_attach
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};
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static int
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macepci_match(parent, match, aux)
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struct device *parent;
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struct cfdata *match;
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void *aux;
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{
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return 1;
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}
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static void
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macepci_attach(parent, self, aux)
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struct device *parent;
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struct device *self;
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void *aux;
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{
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struct macepci_softc *sc = (struct macepci_softc *)self;
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pci_chipset_tag_t pc = &sc->sc_pc;
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struct mace_attach_args *maa = aux;
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struct pcibus_attach_args pba;
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pcitag_t devtag;
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pcireg_t slot;
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u_int32_t control;
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int rev;
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rev = bus_space_read_4(maa->maa_st, maa->maa_sh, MACEPCI_REVISION);
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printf(": rev %d\n", rev);
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#if 0
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mace_intr_establish(maa->maa_intr, IPL_NONE, macepci_intr, sc);
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#endif
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pc->pc_conf_read = macepci_conf_read;
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pc->pc_conf_write = macepci_conf_write;
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/*
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* Fixup O2 PCI slot. Bad hack.
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*/
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devtag = pci_make_tag(0, 0, 3, 0);
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slot = macepci_conf_read(0, devtag, PCI_COMMAND_STATUS_REG);
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slot |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE;
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macepci_conf_write(0, devtag, PCI_COMMAND_STATUS_REG, slot);
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slot = macepci_conf_read(0, devtag, PCI_MAPREG_START);
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if (slot == 0xffffffe1)
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macepci_conf_write(0, devtag, PCI_MAPREG_START, 0x00001000);
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slot = macepci_conf_read(0, devtag, PCI_MAPREG_START + (2 << 2));
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if ((slot & 0xffff0000) == 0) {
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slot += 0x00010000;
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macepci_conf_write(0, devtag, PCI_MAPREG_START + (2 << 2),
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0x00000000);
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}
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/*
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* Enable all MACE PCI interrupts. They will be masked by
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* the CRIME code.
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*/
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control = bus_space_read_4(maa->maa_st, maa->maa_sh, MACEPCI_CONTROL);
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control |= CONTROL_INT_MASK;
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bus_space_write_4(maa->maa_st, maa->maa_sh, MACEPCI_CONTROL, control);
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/* XXX */
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printf("macepci0: ctrl %x\n", *(volatile u_int32_t *)0xbf080008);
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#if NPCI > 0
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memset(&pba, 0, sizeof pba);
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pba.pba_busname = "pci";
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/*XXX*/ pba.pba_iot = 4;
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/*XXX*/ pba.pba_memt = 2;
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pba.pba_dmat = &pci_bus_dma_tag;
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pba.pba_bus = 0;
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pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED |
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PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY;
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pba.pba_pc = pc;
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#ifdef MACEPCI_IO_WAS_BUGGY
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if (rev == 0)
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pba.pba_flags &= ~PCI_FLAGS_IO_ENABLED; /* Buggy? */
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#endif
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config_found(self, &pba, macepci_print);
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#endif
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}
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static int
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macepci_print(aux, pnp)
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void *aux;
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const char *pnp;
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{
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struct pcibus_attach_args *pba = aux;
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if (pnp != 0)
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printf("%s at %s", pba->pba_busname, pnp);
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else
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printf(" bus %d", pba->pba_bus);
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/* Mega XXX */
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*(volatile u_int32_t *)0xb4000034 = 0; /* prime timer */
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return UNCONF;
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}
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#define PCI_CFG_ADDR ((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1f080cf8))
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#define PCI_CFG_DATA ((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x1f080cfc))
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pcireg_t
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macepci_conf_read(pc, tag, reg)
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pci_chipset_tag_t pc;
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pcitag_t tag;
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int reg;
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{
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pcireg_t data;
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#if 1
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/* XXX more generic pci error checking */
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if ((*(volatile u_int32_t *)0xbf080004 & ~0x00100000) != 6)
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panic("pcierr: %x %x", *(volatile u_int32_t *)0xbf080004,
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*(volatile u_int32_t *)0xbf080000);
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#endif
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*PCI_CFG_ADDR = tag | reg;
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data = *PCI_CFG_DATA;
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*PCI_CFG_ADDR = 0;
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if (*(volatile u_int32_t *)0xbf080004 & 0xf0000000) {
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*(volatile u_int32_t *)0xbf080004 = 0;
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return (pcireg_t)-1;
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}
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return data;
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}
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void
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macepci_conf_write(pc, tag, reg, data)
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pci_chipset_tag_t pc;
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pcitag_t tag;
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int reg;
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pcireg_t data;
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{
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/* XXX O2 soren */
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if (tag == 0)
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return;
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*PCI_CFG_ADDR = tag | reg;
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*PCI_CFG_DATA = data;
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*PCI_CFG_ADDR = 0;
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}
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/*
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* Handle PCI error interrupts.
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*/
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int
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macepci_intr(arg)
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void *arg;
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{
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return 0;
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}
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