369 lines
12 KiB
C
369 lines
12 KiB
C
/* $NetBSD: cpufunc.h,v 1.9 2001/10/14 00:17:26 bjh21 Exp $ */
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/*
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* Copyright (c) 1997 Mark Brinicombe.
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* Copyright (c) 1997 Causality Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Causality Limited.
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* 4. The name of Causality Limited may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RiscBSD kernel project
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*
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* cpufunc.h
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*
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* Prototypes for cpu, mmu and tlb related functions.
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*/
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#ifndef _ARM32_CPUFUNC_H_
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#define _ARM32_CPUFUNC_H_
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#include <sys/types.h>
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#ifdef _KERNEL
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#ifndef _LKM
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#include "opt_cputypes.h"
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#endif
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struct cpu_functions {
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/* CPU functions */
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u_int (*cf_id) __P((void));
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/* MMU functions */
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u_int (*cf_control) __P((u_int bic, u_int eor));
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void (*cf_domains) __P((u_int domains));
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void (*cf_setttb) __P((u_int ttb));
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u_int (*cf_faultstatus) __P((void));
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u_int (*cf_faultaddress) __P((void));
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/* TLB functions */
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void (*cf_tlb_flushID) __P((void));
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void (*cf_tlb_flushID_SE) __P((u_int va));
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void (*cf_tlb_flushI) __P((void));
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void (*cf_tlb_flushI_SE) __P((u_int va));
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void (*cf_tlb_flushD) __P((void));
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void (*cf_tlb_flushD_SE) __P((u_int va));
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/* Cache functions */
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void (*cf_cache_flushID) __P((void));
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void (*cf_cache_flushID_SE) __P((u_int va));
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void (*cf_cache_flushI) __P((void));
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void (*cf_cache_flushI_SE) __P((u_int va));
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void (*cf_cache_flushD) __P((void));
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void (*cf_cache_flushD_SE) __P((u_int va));
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void (*cf_cache_cleanID) __P((void));
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void (*cf_cache_cleanID_E) __P((u_int imp));
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void (*cf_cache_cleanD) __P((void));
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void (*cf_cache_cleanD_E) __P((u_int imp));
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void (*cf_cache_purgeID) __P((void));
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void (*cf_cache_purgeID_E) __P((u_int imp));
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void (*cf_cache_purgeD) __P((void));
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void (*cf_cache_purgeD_E) __P((u_int imp));
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/* Other functions */
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void (*cf_flush_prefetchbuf) __P((void));
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void (*cf_drain_writebuf) __P((void));
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void (*cf_flush_brnchtgt_C) __P((void));
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void (*cf_flush_brnchtgt_E) __P((u_int va));
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void (*cf_sleep) __P((int mode));
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/* Soft functions */
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void (*cf_cache_syncI) __P((void));
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void (*cf_cache_cleanID_rng) __P((u_int start, u_int len));
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void (*cf_cache_cleanD_rng) __P((u_int start, u_int len));
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void (*cf_cache_purgeID_rng) __P((u_int start, u_int len));
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void (*cf_cache_purgeD_rng) __P((u_int start, u_int len));
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void (*cf_cache_syncI_rng) __P((u_int start, u_int len));
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int (*cf_dataabt_fixup) __P((void *arg));
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int (*cf_prefetchabt_fixup) __P((void *arg));
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void (*cf_context_switch) __P((void));
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void (*cf_setup) __P((char *string));
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};
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extern struct cpu_functions cpufuncs;
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extern u_int cputype;
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#define cpu_id() cpufuncs.cf_id()
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#define cpu_control(c, e) cpufuncs.cf_control(c, e)
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#define cpu_domains(d) cpufuncs.cf_domains(d)
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#define cpu_setttb(t) cpufuncs.cf_setttb(t)
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#define cpu_faultstatus() cpufuncs.cf_faultstatus()
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#define cpu_faultaddress() cpufuncs.cf_faultaddress()
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#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID()
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#define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e)
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#define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI()
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#define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e)
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#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD()
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#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e)
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#define cpu_cache_flushID() cpufuncs.cf_cache_flushID()
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#define cpu_cache_flushID_SE(e) cpufuncs.cf_cache_flushID_SE(e)
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#define cpu_cache_flushI() cpufuncs.cf_cache_flushI()
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#define cpu_cache_flushI_SE(e) cpufuncs.cf_cache_flushI_SE(e)
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#define cpu_cache_flushD() cpufuncs.cf_cache_flushD()
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#define cpu_cache_flushD_SE(e) cpufuncs.cf_cache_flushD_SE(e)
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#define cpu_cache_cleanID() cpufuncs.cf_cache_cleanID()
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#define cpu_cache_cleanID_E(e) cpufuncs.cf_cache_cleanID_E(e)
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#define cpu_cache_cleanD() cpufuncs.cf_cache_cleanD()
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#define cpu_cache_cleanD_E(e) cpufuncs.cf_cache_cleanD_E(e)
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#define cpu_cache_purgeID() cpufuncs.cf_cache_purgeID()
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#define cpu_cache_purgeID_E(e) cpufuncs.cf_cache_purgeID_E(e)
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#define cpu_cache_purgeD() cpufuncs.cf_cache_purgeD()
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#define cpu_cache_purgeD_E(e) cpufuncs.cf_cache_purgeD_E(e)
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#define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf()
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#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf()
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#define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C()
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#define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e)
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#define cpu_sleep(m) cpufuncs.cf_sleep(m)
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#define cpu_cache_syncI() cpufuncs.cf_cache_syncI()
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#define cpu_cache_cleanID_rng(s,l) cpufuncs.cf_cache_cleanID_rng(s,l)
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#define cpu_cache_cleanD_rng(s,l) cpufuncs.cf_cache_cleanD_rng(s,l)
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#define cpu_cache_purgeID_rng(s,l) cpufuncs.cf_cache_purgeID_rng(s,l)
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#define cpu_cache_purgeD_rng(s,l) cpufuncs.cf_cache_purgeD_rng(s,l)
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#define cpu_cache_syncI_rng(s,l) cpufuncs.cf_cache_syncI_rng(s,l)
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#define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a)
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#define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a)
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#define ABORT_FIXUP_OK 0 /* fixup succeeded */
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#define ABORT_FIXUP_FAILED 1 /* fixup failed */
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#define ABORT_FIXUP_RETURN 2 /* abort handler should return */
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#define cpu_setup(a) cpufuncs.cf_setup(a)
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int set_cpufuncs __P((void));
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#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */
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#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */
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void cpufunc_nullop __P((void));
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int cpufunc_null_fixup __P((void *));
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int early_abort_fixup __P((void *));
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int late_abort_fixup __P((void *));
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u_int cpufunc_id __P((void));
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u_int cpufunc_control __P((u_int clear, u_int bic));
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void cpufunc_domains __P((u_int domains));
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u_int cpufunc_faultstatus __P((void));
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u_int cpufunc_faultaddress __P((void));
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#ifdef CPU_ARM3
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u_int arm3_control __P((u_int clear, u_int bic));
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void arm3_cache_flush __P((void));
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#endif /* CPU_ARM3 */
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#if defined(CPU_ARM6) || defined(CPU_ARM7)
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void arm67_setttb __P((u_int ttb));
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void arm67_tlb_flush __P((void));
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void arm67_tlb_purge __P((u_int va));
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void arm67_cache_flush __P((void));
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void arm67_context_switch __P((void));
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#endif /* CPU_ARM6 || CPU_ARM7 */
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#ifdef CPU_ARM6
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void arm6_setup __P((char *string));
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#endif /* CPU_ARM6 */
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#ifdef CPU_ARM7
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void arm7_setup __P((char *string));
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#endif /* CPU_ARM7 */
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#ifdef CPU_ARM7TDMI
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int arm7_dataabt_fixup __P((void *arg));
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void arm7tdmi_setup __P((char *string));
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void arm7tdmi_setttb __P((u_int ttb));
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void arm7tdmi_tlb_flushID __P((void));
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void arm7tdmi_tlb_flushID_SE __P((u_int va));
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void arm7tdmi_cache_flushID __P((void));
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void arm7tdmi_context_switch __P((void));
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#endif /* CPU_ARM7TDMI */
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#ifdef CPU_ARM8
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void arm8_setttb __P((u_int ttb));
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void arm8_tlb_flushID __P((void));
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void arm8_tlb_flushID_SE __P((u_int va));
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void arm8_cache_flushID __P((void));
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void arm8_cache_flushID_E __P((u_int entry));
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void arm8_cache_cleanID __P((void));
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void arm8_cache_cleanID_E __P((u_int entry));
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void arm8_cache_purgeID __P((void));
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void arm8_cache_purgeID_E __P((u_int entry));
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void arm8_cache_syncI __P((void));
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void arm8_cache_cleanID_rng __P((u_int start, u_int end));
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void arm8_cache_cleanD_rng __P((u_int start, u_int end));
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void arm8_cache_purgeID_rng __P((u_int start, u_int end));
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void arm8_cache_purgeD_rng __P((u_int start, u_int end));
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void arm8_cache_syncI_rng __P((u_int start, u_int end));
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void arm8_context_switch __P((void));
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void arm8_setup __P((char *string));
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u_int arm8_clock_config __P((u_int, u_int));
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#endif
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#ifdef CPU_SA110
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void sa110_setttb __P((u_int ttb));
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void sa110_tlb_flushID __P((void));
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void sa110_tlb_flushID_SE __P((u_int va));
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void sa110_tlb_flushI __P((void));
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void sa110_tlb_flushD __P((void));
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void sa110_tlb_flushD_SE __P((u_int va));
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void sa110_cache_flushID __P((void));
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void sa110_cache_flushI __P((void));
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void sa110_cache_flushD __P((void));
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void sa110_cache_flushD_SE __P((u_int entry));
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void sa110_cache_cleanID __P((void));
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void sa110_cache_cleanD __P((void));
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void sa110_cache_cleanD_E __P((u_int entry));
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void sa110_cache_purgeID __P((void));
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void sa110_cache_purgeID_E __P((u_int entry));
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void sa110_cache_purgeD __P((void));
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void sa110_cache_purgeD_E __P((u_int entry));
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void sa110_drain_writebuf __P((void));
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void sa110_cache_syncI __P((void));
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void sa110_cache_cleanID_rng __P((u_int start, u_int end));
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void sa110_cache_cleanD_rng __P((u_int start, u_int end));
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void sa110_cache_purgeID_rng __P((u_int start, u_int end));
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void sa110_cache_purgeD_rng __P((u_int start, u_int end));
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void sa110_cache_syncI_rng __P((u_int start, u_int end));
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void sa110_context_switch __P((void));
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void sa110_setup __P((char *string));
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#endif /* CPU_SA110 */
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#ifdef CPU_XSCALE
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void xscale_setttb __P((u_int ttb));
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void xscale_tlb_flushID __P((void));
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void xscale_tlb_flushID_SE __P((u_int va));
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void xscale_tlb_flushI __P((void));
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void xscale_tlb_flushD __P((void));
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void xscale_tlb_flushD_SE __P((u_int va));
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void xscale_cache_flushID __P((void));
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void xscale_cache_flushI __P((void));
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void xscale_cache_flushD __P((void));
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void xscale_cache_flushD_SE __P((u_int entry));
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void xscale_cache_cleanID __P((void));
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void xscale_cache_cleanD __P((void));
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void xscale_cache_cleanD_E __P((u_int entry));
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void xscale_cache_purgeID __P((void));
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void xscale_cache_purgeID_E __P((u_int entry));
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void xscale_cache_purgeD __P((void));
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void xscale_cache_purgeD_E __P((u_int entry));
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void xscale_drain_writebuf __P((void));
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void xscale_cache_syncI __P((void));
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void xscale_cache_cleanID_rng __P((u_int start, u_int end));
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void xscale_cache_cleanD_rng __P((u_int start, u_int end));
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void xscale_cache_purgeID_rng __P((u_int start, u_int end));
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void xscale_cache_purgeD_rng __P((u_int start, u_int end));
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void xscale_cache_syncI_rng __P((u_int start, u_int end));
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void xscale_context_switch __P((void));
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void xscale_setup __P((char *string));
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#endif /* CPU_XSCALE */
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#define tlb_flush cpu_tlb_flushID
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#define setttb cpu_setttb
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#define cache_clean cpu_cache_purgeID
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#define sync_caches cpu_cache_syncI
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#define sync_icache cpu_cache_syncI
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#define drain_writebuf cpu_drain_writebuf
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/*
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* Macros for manipulating CPU interrupts
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*/
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#define disable_interrupts(mask) \
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(SetCPSR((mask) & (I32_bit | F32_bit), (mask) & (I32_bit | F32_bit)))
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#define enable_interrupts(mask) \
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(SetCPSR((mask) & (I32_bit | F32_bit), 0))
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#define restore_interrupts(old_cpsr) \
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(SetCPSR((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit)))
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/*
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* Functions to manipulate the CPSR
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* (in arm/arm32/setcpsr.S)
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*/
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u_int SetCPSR __P((u_int bic, u_int eor));
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u_int GetCPSR __P((void));
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/*
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* Functions to manipulate cpu r13
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* (in arm/arm32/setstack.S)
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*/
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void set_stackptr __P((u_int mode, u_int address));
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u_int get_stackptr __P((u_int mode));
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/*
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* Miscellany
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*/
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int get_pc_str_offset __P((void));
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/*
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* CPU functions from locore.S
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*/
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void cpu_reset __P((void)) __attribute__((__noreturn__));
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#endif /* _KERNEL */
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#endif /* _ARM32_CPUFUNC_H_ */
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/* End of cpufunc.h */
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