97 lines
2.9 KiB
C
97 lines
2.9 KiB
C
/* $NetBSD: p5reg.h,v 1.1 2000/05/25 22:12:00 is Exp $ */
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/*
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* Copyright (C) 2000 Adam Ciarcinski.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Adam Ciarcinski for
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* the NetBSD project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _P5REG_H_
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#define _P5REG_H_
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#define P5BASE 0xf60000
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/* registers */
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#define P5_REG_RESET 0x00
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#define P5_REG_ENABLE 0x08
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#define P5_REG_WAITSTATE 0x10
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#define P5_REG_SHADOW 0x18
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#define P5_REG_LOCK 0x20
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#define P5_REG_INT 0x28
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#define P5_IPL_EMU 0x30
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#define P5_INT_LVL 0x38
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/* bit definitions */
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#define P5_SET_CLEAR 0x80
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/* REQ_RESET */
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#define P5_PPC_RESET 0x10
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#define P5_M68K_RESET 0x08
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#define P5_AMIGA_RESET 0x04
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#define P5_AUX_RESET 0x02
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#define P5_SCSI_RESET 0x01
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/* REG_WAITSTATE */
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#define P5_PPC_WRITE 0x08
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#define P5_PPC_READ 0x04
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#define P5_M68K_WRITE 0x02
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#define P5_M68K_READ 0x01
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/* REG_SHADOW */
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#define P5_SELF_RESET 0x40
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#define P5_SHADOW 0x01
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/* REG_LOCK */
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#define P5_MAGIC1 0x40
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#define P5_MAGIC2 0x20
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#define P5_MAGIC3 0x10
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/* REG_INT */
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#define P5_ENABLE_IPL 0x02
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#define P5_INT_MASTER 0x01
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/* IPL_EMU */
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#define P5_DISABLE_INT 0x40
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#define P5_M68K_IPL2 0x20
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#define P5_M68K_IPL1 0x10
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#define P5_M68K_IPL0 0x08
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#define P5_PPC_IPL2 0x04
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#define P5_PPC_IPL1 0x02
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#define P5_PPC_IPL0 0x01
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/* INT_LVL */
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#define P5_LVL7 0x40
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#define P5_LVL6 0x20
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#define P5_LVL5 0x10
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#define P5_LVL4 0x08
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#define P5_LVL3 0x04
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#define P5_LVL2 0x02
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#define P5_LVL1 0x01
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#endif /* _P5REG_H_ */
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