932f692851
This controller is integrated in some ALi Southbridges. XXX This driver is incomplete and slightly buggy, but it works enough to enable me to listen to music on my Sharp MM20.
161 lines
7.0 KiB
C
161 lines
7.0 KiB
C
/* $NetBSD: auacerreg.h,v 1.1 2004/10/10 16:37:07 augustss Exp $ */
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/*-
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* Copyright (c) 2004 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Lennart Augustsson.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_PCI_AUACERREG_H_
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#define _DEV_PCI_AUACERREG_H_
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#define ALI_SCR 0x00 /* System Control Register */
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#define ALI_SCR_RESET (1<<31) /* master reset */
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#define ALI_SCR_AC97_DBL (1<<30)
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#define ALI_SCR_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
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#define ALI_SCR_IN_BITS (3<<18)
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#define ALI_SCR_OUT_BITS (3<<16)
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#define ALI_SCR_6CH_CFG (3<<14)
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#define ALI_SCR_PCM_4 (1<<8)
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#define ALI_SCR_PCM_6 (2<<8)
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#define ALI_SCR_PCM_246_MASK (ALI_SCR_PCM_4 | ALI_SCR_PCM_6)
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#define ALI_SSR 0x04 /* System Status Register */
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#define ALI_SSR_SEC_ID (3<<5)
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#define ALI_SSR_PRI_ID (3<<3)
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#define ALI_DMACR 0x08 /* DMA Control Register */
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#define ALI_DMACR_PAUSE 16 /* offset for pause bits */
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#define ALI_FIFOCR1 0x0c /* FIFO Control Register 1 */
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#define ALI_INTERFACECR 0x10 /* Interface Control Register */
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#define ALI_INTERRUPTCR 0x14 /* Interrupt Control Register */
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#define ALI_INTERRUPTSR 0x18 /* Interrupt Status Register */
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#define ALI_INT_MICIN2 (1<<26)
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#define ALI_INT_PCMIN2 (1<<25)
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#define ALI_INT_I2SIN (1<<24)
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#define ALI_INT_SPDIFOUT (1<<23)
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#define ALI_INT_SPDIFIN (1<<22)
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#define ALI_INT_LFEOUT (1<<21)
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#define ALI_INT_CENTEROUT (1<<20)
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#define ALI_INT_CODECSPDIFOUT (1<<19)
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#define ALI_INT_MICIN (1<<18)
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#define ALI_INT_PCMOUT (1<<17)
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#define ALI_INT_PCMIN (1<<16)
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#define ALI_INT_CPRAIS (1<<7)
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#define ALI_INT_SPRAIS (1<<5)
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#define ALI_INT_GPIO (1<<1)
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#define ALI_FIFOCR2 0x1c /* FIFO Control Register 2 */
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#define ALI_CPR 0x20 /* Command Port Register */
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#define ALI_CPR_ADDR_SECONDARY 0x100
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#define ALI_CPR_ADDR_READ 0x80
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#define ALI_CPR_ADDR 0x22 /* AC97 write addr */
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#define ALI_SPR 0x24 /* Status Port Register */
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#define ALI_SPR_ADDR 0x26 /* AC97 read addr */
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#define ALI_FIFOCR3 0x2c /* FIFO Control Register 3 */
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#define ALI_TTSR 0x30 /* Transmit Tag Slot Register */
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#define ALI_RTSR 0x34 /* Receive Tag Slot Register */
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#define ALI_CSPSR 0x38 /* Command/Status Port Status Register */
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#define ALI_CSPSR_CODEC_READY 0x08
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#define ALI_CSPSR_READ_OK 0x02
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#define ALI_CSPSR_WRITE_OK 0x01
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#define ALI_CAS 0x3c /* Codec Write Semaphore Register */
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#define ALI_CAS_SEM_BUSY 0x80000000
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#define ALI_HWVOL 0xf0 /* hardware volume control/status */
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#define ALI_I2SCR 0xf4 /* I2S control/status */
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#define ALI_SPDIFCSR 0xf8 /* SPDIF Channel Status Register */
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#define ALI_SPDIFICS 0xfc /* SPDIF Interface Control/Status */
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#define ALI_OFF_BDBAR 0x00 /* Buffer Descriptor list Base Address */
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#define ALI_OFF_CIV 0x04 /* Current Index Value */
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#define ALI_OFF_LVI 0x05 /* Last Valid Index */
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#define ALI_LVI_MASK 0x1f
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#define ALI_OFF_SR 0x06 /* Status Register */
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#define ALI_SR_DMA_INT_FIFO (1<<4) /* fifo under/over flow */
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#define ALI_SR_DMA_INT_COMPLETE (1<<3) /* buffer read/write complete and ioc set */
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#define ALI_SR_DMA_INT_LVI (1<<2) /* last valid done */
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#define ALI_SR_DMA_INT_CELV (1<<1) /* last valid is current */
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#define ALI_SR_DMA_INT_DCH (1<<0) /* DMA Controller Halted (happens on LVI interrupts) */
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#define ALI_SR_W1TC (ALI_SR_DMA_INT_LVI | ALI_SR_DMA_INT_COMPLETE | ALI_SR_DMA_INT_FIFO | ALI_SR_DMA_INT_CELV)
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#define ALI_OFF_PICB 0x08 /* Position In Current Buffer */
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#define ALI_PIV 0x0a /* 5 bits prefetched index value */
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#define ALI_OFF_CR 0x0b /* Control Register */
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#define ALI_CR_IOCE 0x10 /* Int On Completion Enable */
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#define ALI_CR_FEIE 0x08 /* Fifo Error Int Enable */
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#define ALI_CR_LVBIE 0x04 /* Last Valid Buf Int Enable */
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#define ALI_CR_RR 0x02 /* 1 - Reset Regs */
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#define ALI_CR_RPBM 0x01 /* 1 - Run, 0 - Pause */
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#define ALI_BASE_PI 0x40 /* PCM In */
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#define ALI_BASE_PO 0x50 /* PCM Out */
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#define ALI_BASE_MC 0x60 /* Mic In */
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#define ALI_BASE_CODEC_SPDIFO 0x70 /* Codec SPDIF Out */
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#define ALI_BASE_CENTER 0x80 /* Center out */
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#define ALI_BASE_LFE 0x90 /* ? */
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#define ALI_BASE_CTL_SPDIFI 0xa0 /* Controller SPDIF In */
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#define ALI_BASE_CTL_SPDIFO 0xb0 /* Controller SPDIF Out */
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#define ALI_PORT2SLOT(port) (((port) - 0x40) / 0x10)
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#define ALI_PORT2INTR(port) (ALI_PORT2SLOT(port) + 16)
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#define ALI_IF_AC97SP (1<<21)
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#define ALI_IF_MC (1<<20)
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#define ALI_IF_PI (1<<19)
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#define ALI_IF_MC2 (1<<18)
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#define ALI_IF_PI2 (1<<17)
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#define ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
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#define ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
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#define ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
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#define ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
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#define ALI_IF_PO_SPDF (1<<3)
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#define ALI_IF_PO (1<<1)
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#define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
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#define ALI_SAMPLE_SIZE 2
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/*
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* according to the dev/audiovar.h AU_RING_SIZE is 2^16, what fits
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* in our limits perfectly, i.e. setting it to higher value
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* in your kernel config would improve perfomance, still 2^21 is the max
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*/
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#define ALI_DMALIST_MAX 32
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#define ALI_DMASEG_MAX (65536*2) /* 64k samples, 2x16 bit samples */
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struct auacer_dmalist {
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u_int32_t base;
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u_int32_t len;
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#define ALI_DMAF_IOC 0x80000000 /* 1-int on complete */
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#define ALI_DMAF_BUP 0x40000000 /* 0-retrans last, 1-transmit 0 */
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};
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#endif /* _DEV_PCI_AUACERREG_H_ */
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