587 lines
18 KiB
C
587 lines
18 KiB
C
/* $NetBSD: pmap.h,v 1.7 2002/12/03 22:03:01 fvdl Exp $ */
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/*
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*
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* Copyright (c) 1997 Charles D. Cranor and Washington University.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgment:
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* This product includes software developed by Charles D. Cranor and
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* Washington University.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Frank van der Linden for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* pmap.h: see pmap.c for the history of this pmap module.
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*/
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#ifndef _X86_64_PMAP_H_
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#define _X86_64_PMAP_H_
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#ifndef _LOCORE
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#if defined(_KERNEL_OPT)
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#include "opt_largepages.h"
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#endif
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#include <machine/cpufunc.h>
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#include <machine/pte.h>
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#include <machine/segments.h>
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#include <uvm/uvm_object.h>
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#endif
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/*
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* The x86_64 pmap module closely resembles the i386 one. It uses
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* the same recursive entry scheme, and the same alternate area
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* trick for accessing non-current pmaps. See the i386 pmap.h
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* for a description. The obvious difference is that 3 extra
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* levels of page table need to be dealt with. The level 1 page
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* table pages are at:
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*
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* l1: 0x00007f8000000000 - 0x00007fffffffffff (39 bits, needs PML4 entry)
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*
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* The alternate space is at:
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*
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* l1: 0xffffff8000000000 - 0xffffffffffffffff (39 bits, needs PML4 entry)
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*
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* The rest is kept as physical pages in 3 UVM objects, and is
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* temporarily mapped for virtual access when needed.
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*
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* Note that address space is signed, so the layout for 48 bits is:
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*
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* +---------------------------------+ 0xffffffffffffffff
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* | |
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* | alt.L1 table (PTE pages) |
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* | |
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* +---------------------------------+ 0xffffff8000000000
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* ~ ~
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* | |
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* | Kernel Space |
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* | |
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* | |
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* +---------------------------------+ 0xffff800000000000 = 0x0000008000000000
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* | |
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* | alt.L1 table (PTE pages) |
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* | |
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* +---------------------------------+ 0x00007f8000000000
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* ~ ~
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* | |
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* | User Space |
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* | |
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* | |
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* +---------------------------------+ 0x0000000000000000
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*
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* In other words, there is a 'VA hole' at 0x0000008000000000 -
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* 0xffff800000000000 which will trap, just as on, for example,
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* sparcv9.
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*
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* The unused space can be used if needed, but it adds a little more
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* complexity to the calculations.
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*/
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/*
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* The first generation of Hammer processors can use 48 bits of
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* virtual memory, and 40 bits of physical memory. This will be
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* more for later generations. These defines can be changed to
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* variable names containing the # of bits, extracted from an
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* extended cpuid instruction (variables are harder to use during
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* bootstrap, though)
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*/
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#define VIRT_BITS 48
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#define PHYS_BITS 40
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/*
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* Mask to get rid of the sign-extended part of addresses.
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*/
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#define VA_SIGN_MASK 0xffff000000000000
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#define VA_SIGN_NEG(va) ((va) | VA_SIGN_MASK)
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/*
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* XXXfvdl this one's not right.
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*/
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#define VA_SIGN_POS(va) ((va) & ~VA_SIGN_MASK)
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#define L4_SLOT_PTE 255
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#define L4_SLOT_KERN 256
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#define L4_SLOT_KERNBASE 511
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#define L4_SLOT_APTE 510
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#define PDIR_SLOT_KERN L4_SLOT_KERN
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#define PDIR_SLOT_PTE L4_SLOT_PTE
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#define PDIR_SLOT_APTE L4_SLOT_APTE
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/*
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* the following defines give the virtual addresses of various MMU
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* data structures:
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* PTE_BASE and APTE_BASE: the base VA of the linear PTE mappings
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* PTD_BASE and APTD_BASE: the base VA of the recursive mapping of the PTD
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* PDP_PDE and APDP_PDE: the VA of the PDE that points back to the PDP/APDP
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*
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*/
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#define PTE_BASE ((pt_entry_t *) (L4_SLOT_PTE * NBPD_L4))
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#define APTE_BASE ((pt_entry_t *) (VA_SIGN_NEG((L4_SLOT_APTE * NBPD_L4))))
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#define L1_BASE PTE_BASE
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#define AL1_BASE APTE_BASE
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#define L2_BASE ((pd_entry_t *)((char *)L1_BASE + L4_SLOT_PTE * NBPD_L3))
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#define L3_BASE ((pd_entry_t *)((char *)L2_BASE + L4_SLOT_PTE * NBPD_L2))
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#define L4_BASE ((pd_entry_t *)((char *)L3_BASE + L4_SLOT_PTE * NBPD_L1))
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#define AL2_BASE ((pd_entry_t *)((char *)AL1_BASE + L4_SLOT_PTE * NBPD_L3))
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#define AL3_BASE ((pd_entry_t *)((char *)AL2_BASE + L4_SLOT_PTE * NBPD_L2))
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#define AL4_BASE ((pd_entry_t *)((char *)AL3_BASE + L4_SLOT_PTE * NBPD_L1))
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#define PDP_PDE (L4_BASE + PDIR_SLOT_PTE)
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#define APDP_PDE (L4_BASE + PDIR_SLOT_APTE)
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#define PDP_BASE L4_BASE
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#define APDP_BASE AL4_BASE
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#define NKL4_MAX_ENTRIES (unsigned long)1
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#define NKL3_MAX_ENTRIES (unsigned long)(NKL4_MAX_ENTRIES * 512)
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#define NKL2_MAX_ENTRIES (unsigned long)(NKL3_MAX_ENTRIES * 512)
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#define NKL1_MAX_ENTRIES (unsigned long)(NKL2_MAX_ENTRIES * 512)
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#define NKL4_KIMG_ENTRIES 1
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#define NKL3_KIMG_ENTRIES 1
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#define NKL2_KIMG_ENTRIES 4
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/*
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* Since kva space is below the kernel in its entirety, we start off
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* with zero entries on each level.
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*/
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#define NKL4_START_ENTRIES 0
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#define NKL3_START_ENTRIES 0
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#define NKL2_START_ENTRIES 0
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#define NKL1_START_ENTRIES 0 /* XXX */
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#define NTOPLEVEL_PDES (NBPG / (sizeof (pd_entry_t)))
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#define KERNSPACE (NKL4_ENTRIES * NBPD_L4)
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#define NPDPG (NBPG / sizeof (pd_entry_t))
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#define ptei(VA) (((VA_SIGN_POS(VA)) & L1_MASK) >> L1_SHIFT)
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/*
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* pl*_pi: index in the ptp page for a pde mapping a VA.
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* (pl*_i below is the index in the virtual array of all pdes per level)
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*/
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#define pl1_pi(VA) (((VA_SIGN_POS(VA)) & L1_MASK) >> L1_SHIFT)
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#define pl2_pi(VA) (((VA_SIGN_POS(VA)) & L2_MASK) >> L2_SHIFT)
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#define pl3_pi(VA) (((VA_SIGN_POS(VA)) & L3_MASK) >> L3_SHIFT)
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#define pl4_pi(VA) (((VA_SIGN_POS(VA)) & L4_MASK) >> L4_SHIFT)
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/*
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* pl*_i: generate index into pde/pte arrays in virtual space
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*/
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#define pl1_i(VA) (((VA_SIGN_POS(VA)) & L1_FRAME) >> L1_SHIFT)
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#define pl2_i(VA) (((VA_SIGN_POS(VA)) & L2_FRAME) >> L2_SHIFT)
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#define pl3_i(VA) (((VA_SIGN_POS(VA)) & L3_FRAME) >> L3_SHIFT)
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#define pl4_i(VA) (((VA_SIGN_POS(VA)) & L4_FRAME) >> L4_SHIFT)
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#define pl_i(va, lvl) \
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(((VA_SIGN_POS(va)) & ptp_masks[(lvl)-1]) >> ptp_shifts[(lvl)-1])
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#define PTP_MASK_INITIALIZER { L1_FRAME, L2_FRAME, L3_FRAME, L4_FRAME }
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#define PTP_SHIFT_INITIALIZER { L1_SHIFT, L2_SHIFT, L3_SHIFT, L4_SHIFT }
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#define NKPTP_INITIALIZER { NKL1_START_ENTRIES, NKL2_START_ENTRIES, \
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NKL3_START_ENTRIES, NKL4_START_ENTRIES }
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#define NKPTPMAX_INITIALIZER { NKL1_MAX_ENTRIES, NKL2_MAX_ENTRIES, \
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NKL3_MAX_ENTRIES, NKL4_MAX_ENTRIES }
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#define NBPD_INITIALIZER { NBPD_L1, NBPD_L2, NBPD_L3, NBPD_L4 }
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#define PDES_INITIALIZER { L2_BASE, L3_BASE, L4_BASE }
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#define APDES_INITIALIZER { AL2_BASE, AL3_BASE, AL4_BASE }
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/*
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* PTP macros:
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* a PTP's index is the PD index of the PDE that points to it
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* a PTP's offset is the byte-offset in the PTE space that this PTP is at
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* a PTP's VA is the first VA mapped by that PTP
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*
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* note that NBPG == number of bytes in a PTP (4096 bytes == 1024 entries)
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* NBPD == number of bytes a PTP can map (4MB)
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*/
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#define ptp_va2o(va, lvl) (pl_i(va, (lvl)+1) * NBPG)
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#define PTP_LEVELS 4
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/*
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* PG_AVAIL usage: we make use of the ignored bits of the PTE
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*/
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#define PG_W PG_AVAIL1 /* "wired" mapping */
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#define PG_PVLIST PG_AVAIL2 /* mapping has entry on pvlist */
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/* PG_AVAIL3 not used */
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/*
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* Number of PTE's per cache line. 8 byte pte, 64-byte cache line
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* Used to avoid false sharing of cache lines.
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*/
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#define NPTECL 8
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#if defined(_KERNEL) && !defined(_LOCORE)
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/*
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* pmap data structures: see pmap.c for details of locking.
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*/
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struct pmap;
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typedef struct pmap *pmap_t;
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/*
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* we maintain a list of all non-kernel pmaps
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*/
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LIST_HEAD(pmap_head, pmap); /* struct pmap_head: head of a pmap list */
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/*
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* the pmap structure
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*
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* note that the pm_obj contains the simple_lock, the reference count,
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* page list, and number of PTPs within the pmap.
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*
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* pm_lock is the same as the spinlock for vm object 0. Changes to
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* the other objects may only be made if that lock has been taken
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* (the other object locks are only used when uvm_pagealloc is called)
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*/
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struct pmap {
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struct uvm_object pm_obj[PTP_LEVELS-1]; /* objects for lvl >= 1) */
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#define pm_lock pm_obj[0].vmobjlock
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#define pm_obj_l1 pm_obj[0]
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#define pm_obj_l2 pm_obj[1]
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#define pm_obj_l3 pm_obj[2]
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LIST_ENTRY(pmap) pm_list; /* list (lck by pm_list lock) */
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pd_entry_t *pm_pdir; /* VA of PD (lck by object lock) */
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paddr_t pm_pdirpa; /* PA of PD (read-only after create) */
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struct vm_page *pm_ptphint[PTP_LEVELS-1];
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/* pointer to a PTP in our pmap */
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struct pmap_statistics pm_stats; /* pmap stats (lck by object lock) */
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int pm_flags; /* see below */
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union descriptor *pm_ldt; /* user-set LDT */
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int pm_ldt_len; /* number of LDT entries */
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int pm_ldt_sel; /* LDT selector */
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u_int32_t pm_cpus; /* mask of CPUs using pmap */
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};
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/* pm_flags */
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#define PMF_USER_LDT 0x01 /* pmap has user-set LDT */
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/*
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* for each managed physical page we maintain a list of <PMAP,VA>'s
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* which it is mapped at. the list is headed by a pv_head structure.
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* there is one pv_head per managed phys page (allocated at boot time).
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* the pv_head structure points to a list of pv_entry structures (each
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* describes one mapping).
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*/
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struct pv_entry;
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struct pv_head {
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struct simplelock pvh_lock; /* locks every pv on this list */
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struct pv_entry *pvh_list; /* head of list (locked by pvh_lock) */
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};
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struct pv_entry { /* locked by its list's pvh_lock */
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struct pv_entry *pv_next; /* next entry */
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struct pmap *pv_pmap; /* the pmap */
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vaddr_t pv_va; /* the virtual address */
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struct vm_page *pv_ptp; /* the vm_page of the PTP */
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};
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/*
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* pv_entrys are dynamically allocated in chunks from a single page.
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* we keep track of how many pv_entrys are in use for each page and
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* we can free pv_entry pages if needed. there is one lock for the
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* entire allocation system.
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*/
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struct pv_page_info {
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TAILQ_ENTRY(pv_page) pvpi_list;
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struct pv_entry *pvpi_pvfree;
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int pvpi_nfree;
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};
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/*
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* number of pv_entry's in a pv_page
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* (note: won't work on systems where NPBG isn't a constant)
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*/
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#define PVE_PER_PVPAGE ((NBPG - sizeof(struct pv_page_info)) / \
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sizeof(struct pv_entry))
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/*
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* a pv_page: where pv_entrys are allocated from
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*/
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struct pv_page {
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struct pv_page_info pvinfo;
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struct pv_entry pvents[PVE_PER_PVPAGE];
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};
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/*
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* pmap_remove_record: a record of VAs that have been unmapped, used to
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* flush TLB. if we have more than PMAP_RR_MAX then we stop recording.
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*/
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#define PMAP_RR_MAX 16 /* max of 16 pages (64K) */
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struct pmap_remove_record {
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int prr_npages;
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vaddr_t prr_vas[PMAP_RR_MAX];
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};
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/*
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* global kernel variables
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*/
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/* PTDpaddr: is the physical address of the kernel's PDP */
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extern u_long PTDpaddr;
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extern struct pmap kernel_pmap_store; /* kernel pmap */
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extern int pmap_pg_g; /* do we support PG_G? */
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extern paddr_t ptp_masks[];
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extern int ptp_shifts[];
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extern unsigned long nkptp[], nbpd[], nkptpmax[];
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extern pd_entry_t *pdes[];
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/*
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* macros
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*/
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#define pmap_kernel() (&kernel_pmap_store)
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#define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count)
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#define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count)
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#define pmap_update(pmap) /* nothing (yet) */
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#define pmap_clear_modify(pg) pmap_clear_attrs(pg, PG_M)
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#define pmap_clear_reference(pg) pmap_clear_attrs(pg, PG_U)
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#define pmap_copy(DP,SP,D,L,S)
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#define pmap_is_modified(pg) pmap_test_attrs(pg, PG_M)
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#define pmap_is_referenced(pg) pmap_test_attrs(pg, PG_U)
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#define pmap_move(DP,SP,D,L,S)
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#define pmap_phys_address(ppn) ptob(ppn)
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#define pmap_valid_entry(E) ((E) & PG_V) /* is PDE or PTE valid? */
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/*
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* prototypes
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*/
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void pmap_activate __P((struct proc *));
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void pmap_bootstrap __P((vaddr_t));
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boolean_t pmap_clear_attrs __P((struct vm_page *, unsigned));
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void pmap_deactivate __P((struct proc *));
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static void pmap_page_protect __P((struct vm_page *, vm_prot_t));
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void pmap_page_remove __P((struct vm_page *));
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static void pmap_protect __P((struct pmap *, vaddr_t,
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vaddr_t, vm_prot_t));
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void pmap_remove __P((struct pmap *, vaddr_t, vaddr_t));
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boolean_t pmap_test_attrs __P((struct vm_page *, unsigned));
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static void pmap_update_pg __P((vaddr_t));
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static void pmap_update_2pg __P((vaddr_t,vaddr_t));
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void pmap_write_protect __P((struct pmap *, vaddr_t,
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vaddr_t, vm_prot_t));
|
|
|
|
vaddr_t reserve_dumppages __P((vaddr_t)); /* XXX: not a pmap fn */
|
|
|
|
void pmap_tlb_shootdown __P((pmap_t, vaddr_t, pt_entry_t, int32_t *));
|
|
void pmap_tlb_shootnow __P((int32_t));
|
|
void pmap_do_tlb_shootdown __P((struct cpu_info *));
|
|
|
|
#define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */
|
|
|
|
/*
|
|
* Do idle page zero'ing uncached to avoid polluting the cache.
|
|
*/
|
|
boolean_t pmap_pageidlezero __P((paddr_t));
|
|
#define PMAP_PAGEIDLEZERO(pa) pmap_pageidlezero((pa))
|
|
|
|
/*
|
|
* inline functions
|
|
*/
|
|
|
|
static __inline void
|
|
pmap_remove_all(struct pmap *pmap)
|
|
{
|
|
/* Nothing. */
|
|
}
|
|
|
|
/*
|
|
* pmap_update_pg: flush one page from the TLB (or flush the whole thing
|
|
* if hardware doesn't support one-page flushing)
|
|
*/
|
|
|
|
__inline static void
|
|
pmap_update_pg(va)
|
|
vaddr_t va;
|
|
{
|
|
invlpg(va);
|
|
}
|
|
|
|
/*
|
|
* pmap_update_2pg: flush two pages from the TLB
|
|
*/
|
|
|
|
__inline static void
|
|
pmap_update_2pg(va, vb)
|
|
vaddr_t va, vb;
|
|
{
|
|
invlpg(va);
|
|
invlpg(vb);
|
|
}
|
|
|
|
/*
|
|
* pmap_page_protect: change the protection of all recorded mappings
|
|
* of a managed page
|
|
*
|
|
* => this function is a frontend for pmap_page_remove/pmap_clear_attrs
|
|
* => we only have to worry about making the page more protected.
|
|
* unprotecting a page is done on-demand at fault time.
|
|
*/
|
|
|
|
__inline static void
|
|
pmap_page_protect(struct vm_page *pg, vm_prot_t prot)
|
|
{
|
|
if ((prot & VM_PROT_WRITE) == 0) {
|
|
if (prot & (VM_PROT_READ|VM_PROT_EXECUTE)) {
|
|
(void) pmap_clear_attrs(pg, PG_RW);
|
|
} else {
|
|
pmap_page_remove(pg);
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* pmap_protect: change the protection of pages in a pmap
|
|
*
|
|
* => this function is a frontend for pmap_remove/pmap_write_protect
|
|
* => we only have to worry about making the page more protected.
|
|
* unprotecting a page is done on-demand at fault time.
|
|
*/
|
|
|
|
__inline static void
|
|
pmap_protect(pmap, sva, eva, prot)
|
|
struct pmap *pmap;
|
|
vaddr_t sva, eva;
|
|
vm_prot_t prot;
|
|
{
|
|
if ((prot & VM_PROT_WRITE) == 0) {
|
|
if (prot & (VM_PROT_READ|VM_PROT_EXECUTE)) {
|
|
pmap_write_protect(pmap, sva, eva, prot);
|
|
} else {
|
|
pmap_remove(pmap, sva, eva);
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* various address inlines
|
|
*
|
|
* vtopte: return a pointer to the PTE mapping a VA, works only for
|
|
* user and PT addresses
|
|
*
|
|
* kvtopte: return a pointer to the PTE mapping a kernel VA
|
|
*/
|
|
|
|
#include <lib/libkern/libkern.h>
|
|
|
|
static __inline pt_entry_t *
|
|
vtopte(vaddr_t va)
|
|
{
|
|
|
|
KASSERT(va < (L4_SLOT_KERN * NBPD_L4));
|
|
|
|
return (PTE_BASE + pl1_i(va));
|
|
}
|
|
|
|
static __inline pt_entry_t *
|
|
kvtopte(vaddr_t va)
|
|
{
|
|
|
|
KASSERT(va >= (L4_SLOT_KERN * NBPD_L4));
|
|
|
|
#ifdef LARGEPAGES
|
|
{
|
|
pd_entry_t *pde;
|
|
|
|
pde = L1_BASE + pl2_i(va);
|
|
if (*pde & PG_PS)
|
|
return ((pt_entry_t *)pde);
|
|
}
|
|
#endif
|
|
|
|
return (PTE_BASE + pl1_i(va));
|
|
}
|
|
|
|
paddr_t vtophys __P((vaddr_t));
|
|
vaddr_t pmap_map __P((vaddr_t, paddr_t, paddr_t, vm_prot_t));
|
|
|
|
#if 0 /* XXXfvdl was USER_LDT, need to check if that can be supported */
|
|
void pmap_ldt_cleanup __P((struct proc *));
|
|
#define PMAP_FORK
|
|
#endif /* USER_LDT */
|
|
|
|
#endif /* _KERNEL && !_LOCORE */
|
|
#endif /* _X86_64_PMAP_H_ */
|