567 lines
14 KiB
C
567 lines
14 KiB
C
/* $NetBSD: vrgiu.c,v 1.6 2000/02/22 04:11:24 sato Exp $ */
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/*-
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* Copyright (c) 1999
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* Shin Takemura and PocketBSD Project. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the PocketBSD project
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* and its contributors.
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* 4. Neither the name of the project nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <sys/queue.h>
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#define TAILQ_FOREACH(var, head, field) \
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for (var = TAILQ_FIRST(head); var; var = TAILQ_NEXT(var, field))
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#define TAILQ_EMPTY(head) ((head)->tqh_first == NULL)
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#include <mips/cpuregs.h>
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#include <machine/bus.h>
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#include <hpcmips/vr/vripreg.h>
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#include <hpcmips/vr/vripvar.h>
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#include <hpcmips/vr/vrgiureg.h>
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#include "locators.h"
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#define VRGIUDEBUG
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#ifdef VRGIUDEBUG
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#define DEBUG_IO 1
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#define DEBUG_INTR 2
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int vrgiu_debug = 1;
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#define DPRINTF(flag, arg) if (vrgiu_debug & flag) printf arg;
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#else
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#define DPRINTF(flag, arg)
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#endif
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#define LEGAL_INTR_PORT(x) ((x) >= 0 && (x) < MAX_GPIO_INOUT)
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#define LEGAL_OUT_PORT(x) ((x) >= 0 && (x) < MAX_GPIO_OUT)
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int vrgiu_match __P((struct device*, struct cfdata*, void*));
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void vrgiu_attach __P((struct device*, struct device*, void*));
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int vrgiu_intr __P((void*));
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int vrgiu_print __P((void*, const char*));
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void vrgiu_callback __P((struct device*));
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void vrgiu_dump_regs(struct vrgiu_softc *sc);
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void vrgiu_dump_iosetting(struct vrgiu_softc *sc);
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u_int32_t vrgiu_regread_4 __P((vrgiu_chipset_tag_t, bus_addr_t));
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u_int16_t vrgiu_regread __P((vrgiu_chipset_tag_t, bus_addr_t));
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void vrgiu_regwrite_4 __P((vrgiu_chipset_tag_t, bus_addr_t, u_int32_t));
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void vrgiu_regwrite __P((vrgiu_chipset_tag_t, bus_addr_t, u_int16_t));
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int vrgiu_port_read __P((vrgiu_chipset_tag_t, int));
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int vrgiu_port_write __P((vrgiu_chipset_tag_t, int, int));
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void *vrgiu_intr_establish __P((vrgiu_chipset_tag_t, int, int, int, int (*)(void *), void*));
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void vrgiu_intr_disestablish __P((vrgiu_chipset_tag_t, void*));
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struct vrgiu_function_tag vrgiu_functions = {
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vrgiu_port_read,
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vrgiu_port_write,
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vrgiu_regread_4,
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vrgiu_regwrite_4,
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vrgiu_intr_establish,
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vrgiu_intr_disestablish
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};
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struct cfattach vrgiu_ca = {
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sizeof(struct vrgiu_softc), vrgiu_match, vrgiu_attach
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};
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int
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vrgiu_match(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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return 2; /* 1st attach group of vrip */
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}
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void
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vrgiu_attach(parent, self, aux)
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struct device *parent;
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struct device *self;
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void *aux;
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{
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struct vrip_attach_args *va = aux;
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struct vrgiu_softc *sc = (void*)self;
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struct gpbus_attach_args gpa;
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int i;
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sc->sc_vc = va->va_vc;
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sc->sc_iot = va->va_iot;
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bus_space_map(sc->sc_iot, va->va_addr, va->va_size,
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0 /* no cache */, &sc->sc_ioh);
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/*
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* Disable all interrupts.
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*/
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sc->sc_intr_mask = 0;
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#ifdef WINCE_DEFAULT_SETTING
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#warning WINCE_DEFAULT_SETTING
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#else
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#ifdef VRGIUDEBUG
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if (vrgiu_debug & DEBUG_IO) {
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printf("\nWIN setting: ");
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vrgiu_dump_iosetting(sc);
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printf("\n");
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}
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#endif /* VRGIUDEBUG */
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vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask);
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#endif
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for (i = 0; i < MAX_GPIO_INOUT; i++)
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TAILQ_INIT(&sc->sc_intr_head[i]);
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if (!(sc->sc_ih = vrip_intr_establish(va->va_vc, va->va_intr, IPL_BIO,
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vrgiu_intr, sc))) {
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printf("%s: can't establish interrupt\n", sc->sc_dev.dv_xname);
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return;
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}
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vrgiu_functions.gf_intr_establish = vrgiu_intr_establish;
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vrgiu_functions.gf_intr_disestablish = vrgiu_intr_disestablish;
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/*
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* Register functions to upper interface.
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*/
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vrip_giu_function_register(va->va_vc, &vrgiu_functions, self);
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#ifdef VRGIUDEBUG
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/* Display port status (Input/Output) for debugging */
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if (vrgiu_debug & DEBUG_IO) {
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u_int32_t preg[2];
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printf("I/O setting: ");
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vrgiu_dump_iosetting(sc);
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printf("\n");
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preg[0] = vrgiu_regread_4(sc, GIUPIOD_REG);
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preg[1] = vrgiu_regread_4(sc, GIUPODAT_REG);
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printf(" data:");
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bitdisp64(preg);
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}
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#endif /* VRGIUDEBUG */
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/*
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* General purpose bus
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*/
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gpa.gpa_busname = "gpbus";
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gpa.gpa_gc = sc;
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gpa.gpa_gf = &vrgiu_functions;
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while (config_found(self, &gpa, vrgiu_print)) ;
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/*
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* GIU-ISA bridge
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*/
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#if 1 /* XXX Sometimes mounting root device failed. Why? XXX*/
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config_defer(self, vrgiu_callback);
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#else
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vrgiu_callback(self);
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#endif
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}
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void
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vrgiu_callback(self)
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struct device *self;
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{
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struct vrgiu_softc *sc = (void*)self;
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struct gpbus_attach_args gpa;
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gpa.gpa_busname = "vrisab";
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gpa.gpa_gc = sc;
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gpa.gpa_gf = &vrgiu_functions;
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config_found(self, &gpa, vrgiu_print);
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}
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int
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vrgiu_print(aux, pnp)
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void *aux;
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const char *pnp;
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{
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if (pnp)
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return (QUIET);
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return (UNCONF);
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}
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void
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vrgiu_dump_iosetting(sc)
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struct vrgiu_softc *sc;
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{
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long iosel, inten, useupdn, termupdn;
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u_int32_t m;
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iosel= vrgiu_regread_4(sc, GIUIOSEL_REG);
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inten= vrgiu_regread_4(sc, GIUINTEN_REG);
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useupdn = vrgiu_regread(sc, GIUUSEUPDN_REG_W);
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termupdn = vrgiu_regread(sc, GIUTERMUPDN_REG_W);
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for (m = 0x80000000; m; m >>=1)
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printf ("%c" , (useupdn&m) ?
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((termupdn&m) ? 'U' : 'D') :
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((iosel&m) ? 'o' : ((inten&m)?'I':'i')));
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}
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void
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vrgiu_dump_regs(sc)
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struct vrgiu_softc *sc;
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{
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if (sc == NULL) {
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panic("%s(%d): VRGIU device not initialized\n",
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__FILE__, __LINE__);
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}
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printf(" IOSEL: %08x\n", vrgiu_regread_4(sc, GIUIOSEL_REG));
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printf(" PIOD: %08x\n", vrgiu_regread_4(sc, GIUPIOD_REG));
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printf(" PODAT: %08x\n", vrgiu_regread_4(sc, GIUPODAT_REG));
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printf(" INTSTAT: %08x\n", vrgiu_regread_4(sc, GIUINTSTAT_REG));
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printf(" INTEN: %08x\n", vrgiu_regread_4(sc, GIUINTEN_REG));
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printf(" INTTYP: %08x\n", vrgiu_regread_4(sc, GIUINTTYP_REG));
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printf(" INTALSEL: %08x\n", vrgiu_regread_4(sc, GIUINTALSEL_REG));
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printf(" INTHTSEL: %08x\n", vrgiu_regread_4(sc, GIUINTHTSEL_REG));
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}
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/*
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* GIU regster access method.
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*/
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u_int32_t
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vrgiu_regread_4(vc, offs)
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vrgiu_chipset_tag_t vc;
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bus_addr_t offs;
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{
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struct vrgiu_softc *sc = (void*)vc;
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u_int16_t reg[2];
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bus_space_read_region_2 (sc->sc_iot, sc->sc_ioh, offs, reg, 2);
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return reg[0]|(reg[1]<<16);
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}
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u_int16_t
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vrgiu_regread(vc, off)
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vrgiu_chipset_tag_t vc;
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bus_addr_t off;
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{
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struct vrgiu_softc *sc = (void*)vc;
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return bus_space_read_2(sc->sc_iot, sc->sc_ioh, off);
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}
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void
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vrgiu_regwrite_4(vc, offs, data)
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vrgiu_chipset_tag_t vc;
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bus_addr_t offs;
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u_int32_t data;
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{
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struct vrgiu_softc *sc = (void*)vc;
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u_int16_t reg[2];
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reg[0] = data & 0xffff;
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reg[1] = (data>>16)&0xffff;
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bus_space_write_region_2 (sc->sc_iot, sc->sc_ioh, offs, reg, 2);
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}
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void
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vrgiu_regwrite(vc, off, data)
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vrgiu_chipset_tag_t vc;
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bus_addr_t off;
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u_int16_t data;
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{
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struct vrgiu_softc *sc = (void*)vc;
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bus_space_write_2(sc->sc_iot, sc->sc_ioh, off, data);
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}
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/*
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* PORT
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*/
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int
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vrgiu_port_read(vc, port)
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vrgiu_chipset_tag_t vc;
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int port;
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{
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int on;
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if (!LEGAL_OUT_PORT(port))
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panic("vrgiu_port_read: illegal gpio port");
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if (port < 32)
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on = (vrgiu_regread_4(vc, GIUPIOD_REG) & (1 << port));
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else
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on = (vrgiu_regread_4(vc, GIUPODAT_REG) & (1 << (port - 32)));
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return (on ? 1 : 0);
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}
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int
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vrgiu_port_write(vc, port, onoff)
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vrgiu_chipset_tag_t vc;
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int port;
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int onoff;
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{
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u_int32_t reg[2];
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int bank;
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if (!LEGAL_OUT_PORT(port))
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panic("vrgiu_port_write: illegal gpio port");
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reg[0] = vrgiu_regread_4(vc, GIUPIOD_REG);
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reg[1] = vrgiu_regread_4(vc, GIUPODAT_REG);
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bank = port < 32 ? 0 : 1;
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if (bank == 1)
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port -= 32;
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if (onoff)
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reg[bank] |= (1<<port);
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else
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reg[bank] &= ~(1<<port);
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vrgiu_regwrite_4(vc, GIUPIOD_REG, reg[0]);
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vrgiu_regwrite_4(vc, GIUPODAT_REG, reg[1]);
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return 0;
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}
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/*
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* For before autoconfiguration.
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*/
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void
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__vrgiu_out(port, data)
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int port;
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int data;
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{
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u_int16_t reg;
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u_int32_t addr;
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int offs;
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if (!LEGAL_OUT_PORT(port))
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panic("__vrgiu_out: illegal gpio port");
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if (port < 16) {
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addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPIOD_L_REG_W));
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offs = port;
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} else if (port < 32) {
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addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPIOD_H_REG_W));
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offs = port - 16;
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} else if (port < 48) {
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addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPODAT_L_REG_W));
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offs = port - 32;
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} else {
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addr = MIPS_PHYS_TO_KSEG1((VRIP_GIU_ADDR + GIUPODAT_H_REG_W));
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offs = port - 48;
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panic ("__vrgiu_out: not coded yet.");
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}
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printf ("__vrgiu_out: addr %08x bit %d\n", addr, offs);
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wbflush();
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reg = *((volatile u_int16_t*)addr);
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if (data) {
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reg |= (1 << offs);
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} else {
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reg &= ~(1 << offs);
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}
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*((volatile u_int16_t*)addr) = reg;
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wbflush();
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}
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/*
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* Interrupt staff
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*/
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void *
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vrgiu_intr_establish(ic, port, mode, level, ih_fun, ih_arg)
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vrgiu_chipset_tag_t ic;
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int port; /* GPIO pin # */
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int mode; /* GIU trigger setting */
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int level; /* XXX not yet */
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int (*ih_fun) __P((void*));
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void *ih_arg;
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{
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struct vrgiu_softc *sc = (void*)ic;
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int s;
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u_int32_t reg, mask;
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struct vrgiu_intr_entry *ih;
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if (!LEGAL_INTR_PORT(port))
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panic ("vrgiu_intr_establish: bogus interrupt line.");
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if (sc->sc_intr_mode[port] && mode != sc->sc_intr_mode[port])
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panic ("vrgiu_intr_establish: bogus interrupt type.");
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else
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sc->sc_intr_mode[port] = mode;
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mask = (1 << port);
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s = splhigh();
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if (!(ih = malloc(sizeof(struct vrgiu_intr_entry), M_DEVBUF, M_NOWAIT)))
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panic ("vrgiu_intr_establish: no memory.");
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ih->ih_port = port;
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ih->ih_fun = ih_fun;
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ih->ih_arg = ih_arg;
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TAILQ_INSERT_TAIL(&sc->sc_intr_head[port], ih, ih_link);
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#ifdef WINCE_DEFAULT_SETTING
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#warning WINCE_DEFAULT_SETTING
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#else
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/*
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* Setup registers
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*/
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/* Input mode */
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reg = vrgiu_regread_4(sc, GIUIOSEL_REG);
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reg &= ~mask;
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vrgiu_regwrite_4(sc, GIUIOSEL_REG, reg);
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/* interrupt type */
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reg = vrgiu_regread_4(sc, GIUINTTYP_REG);
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DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "edge" : "level"));
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if (mode & VRGIU_INTR_EDGE) {
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DPRINTF(DEBUG_INTR, ("edge]"));
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reg |= mask; /* edge */
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} else {
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DPRINTF(DEBUG_INTR, ("level]"));
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reg &= ~mask; /* level */
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}
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vrgiu_regwrite_4(sc, GIUINTTYP_REG, reg);
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/* interrupt level */
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if (!(mode & VRGIU_INTR_EDGE)) {
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reg = vrgiu_regread_4(sc, GIUINTALSEL_REG);
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DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "high" : "low"));
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if (mode & VRGIU_INTR_HIGH) {
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DPRINTF(DEBUG_INTR, ("high]"));
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reg |= mask; /* high */
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} else {
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DPRINTF(DEBUG_INTR, ("low]"));
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reg &= ~mask; /* low */
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}
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vrgiu_regwrite_4(sc, GIUINTALSEL_REG, reg);
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}
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/* hold or through */
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reg = vrgiu_regread_4(sc, GIUINTHTSEL_REG);
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DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "hold" : "through"));
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if (mode & VRGIU_INTR_HOLD) {
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DPRINTF(DEBUG_INTR, ("hold]"));
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reg |= mask; /* hold */
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} else {
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DPRINTF(DEBUG_INTR, ("through]"));
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reg &= ~mask; /* through */
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}
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vrgiu_regwrite_4(sc, GIUINTHTSEL_REG, reg);
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#endif
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/*
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* clear interrupt status
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*/
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reg = vrgiu_regread_4(sc, GIUINTSTAT_REG);
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reg &= ~mask;
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vrgiu_regwrite_4(sc, GIUINTSTAT_REG, reg);
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/*
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* enable interrupt
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*/
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#ifdef WINCE_DEFAULT_SETTING
|
|
#warning WINCE_DEFAULT_SETTING
|
|
#else
|
|
sc->sc_intr_mask |= mask;
|
|
vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask);
|
|
/* Unmask GIU level 2 mask register */
|
|
vrip_intr_setmask2(sc->sc_vc, sc->sc_ih, (1<<port), 1);
|
|
#endif
|
|
splx(s);
|
|
|
|
DPRINTF(DEBUG_INTR, ("\n"));
|
|
#if 0 && defined VRGIUDEBUG
|
|
vrgiu_dump_regs(sc);
|
|
#endif
|
|
|
|
return ih;
|
|
}
|
|
|
|
void
|
|
vrgiu_intr_disestablish(ic, arg)
|
|
vrgiu_chipset_tag_t ic;
|
|
void *arg;
|
|
{
|
|
struct vrgiu_intr_entry *ihe = arg;
|
|
struct vrgiu_softc *sc = (void*)ic;
|
|
int port = ihe->ih_port;
|
|
struct vrgiu_intr_entry *ih;
|
|
int s;
|
|
|
|
s = splhigh();
|
|
TAILQ_FOREACH(ih, &sc->sc_intr_head[port], ih_link) {
|
|
if (ih == ihe) {
|
|
TAILQ_REMOVE(&sc->sc_intr_head[port], ih, ih_link);
|
|
free(ih, M_DEVBUF);
|
|
if (TAILQ_EMPTY(&sc->sc_intr_head[port])) {
|
|
/* Disable interrupt */
|
|
#ifdef WINCE_DEFAULT_SETTING
|
|
#warning WINCE_DEFAULT_SETTING
|
|
#else
|
|
sc->sc_intr_mask &= ~(1<<port);
|
|
vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask);
|
|
#endif
|
|
}
|
|
splx(s);
|
|
return;
|
|
}
|
|
}
|
|
panic("vrgiu_intr_disetablish: no such a handle.");
|
|
/* NOTREACHED */
|
|
}
|
|
|
|
int
|
|
vrgiu_intr(arg)
|
|
void *arg;
|
|
{
|
|
#ifdef DUMP_GIU_LEVEL2_INTR
|
|
#warning DUMP_GIU_LEVEL2_INTR
|
|
static u_int32_t oreg;
|
|
#endif
|
|
struct vrgiu_softc *sc = arg;
|
|
int i;
|
|
u_int32_t reg;
|
|
/* Get Level 2 interrupt status */
|
|
vrip_intr_get_status2 (sc->sc_vc, sc->sc_ih, ®);
|
|
#ifdef DUMP_GIU_LEVEL2_INTR
|
|
#warning DUMP_GIU_LEVEL2_INTR
|
|
{
|
|
u_int32_t uedge, dedge, j;
|
|
for (j = 0x80000000; j > 0; j >>=1)
|
|
printf ("%c" , reg&j ? '|' : '.');
|
|
uedge = (reg ^ oreg) & reg;
|
|
dedge = (reg ^ oreg) & ~reg;
|
|
if (uedge || dedge) {
|
|
for (j = 0; j < 32; j++) {
|
|
if (uedge & (1 << j))
|
|
printf ("+%d", j);
|
|
else if (dedge & (1 << j))
|
|
printf ("-%d", j);
|
|
}
|
|
}
|
|
oreg = reg;
|
|
printf ("\n");
|
|
}
|
|
#endif
|
|
/* Clear interrupt */
|
|
vrgiu_regwrite_4(sc, GIUINTSTAT_REG, vrgiu_regread_4(sc, GIUINTSTAT_REG));
|
|
|
|
/* Dispatch handler */
|
|
for (i = 0; i < MAX_GPIO_INOUT; i++) {
|
|
if (reg & (1 << i)) {
|
|
register struct vrgiu_intr_entry *ih;
|
|
TAILQ_FOREACH(ih, &sc->sc_intr_head[i], ih_link) {
|
|
ih->ih_fun(ih->ih_arg);
|
|
}
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|