303 lines
5.2 KiB
ArmAsm
303 lines
5.2 KiB
ArmAsm
/* $NetBSD: ifpga_io_asm.S,v 1.1 2001/10/27 16:19:08 rearnsha Exp $ */
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/*
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* Copyright (c) 1997 Causality Limited.
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* Copyright (c) 1997 Mark Brinicombe.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe
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* for the NetBSD Project.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* From arm/footbridge/footbridge_io_asm.S
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*/
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#include <machine/asm.h>
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/*
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* bus_space I/O functions for the IFPGA
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*/
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/*
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* Note these functions use ARM Architecture V4 instructions as
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* all IFPGA based systems will be using processors that support
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* V4 or later architectures
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*/
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/*
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* read single
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*/
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ENTRY(ifpga_bs_r_1)
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ldrb r0, [r1, r2]
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mov pc, lr
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ENTRY(ifpga_bs_r_2)
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ldrh r0, [r1, r2]
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mov pc, lr
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ENTRY(ifpga_bs_r_4)
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ldr r0, [r1, r2]
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mov pc, lr
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/*
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* write single
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*/
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ENTRY(ifpga_bs_w_1)
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strb r3, [r1, r2]
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mov pc, lr
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ENTRY(ifpga_bs_w_2)
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strh r3, [r1, r2]
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mov pc, lr
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ENTRY(ifpga_bs_w_4)
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str r3, [r1, r2]
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mov pc, lr
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/*
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* read multiple
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*/
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ENTRY(ifpga_bs_rm_1)
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add r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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moveq pc, lr
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Lifpga_bs_rm_1_loop:
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ldrb r3, [r0]
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strb r3, [r1], #1
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subs r2, r2, #1
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bne Lifpga_bs_rm_1_loop
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mov pc, lr
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ENTRY(ifpga_bs_rm_2)
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add r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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moveq pc, lr
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Lifpga_bs_rm_2_loop:
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ldrh r3, [r0]
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strh r3, [r1], #2
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subs r2, r2, #1
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bne Lifpga_bs_rm_2_loop
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mov pc, lr
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ENTRY(ifpga_bs_rm_4)
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add r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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moveq pc, lr
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Lifpga_bs_rm_4_loop:
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ldr r3, [r0]
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str r3, [r1], #4
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subs r2, r2, #1
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bne Lifpga_bs_rm_4_loop
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mov pc, lr
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/*
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* write multiple
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*/
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ENTRY(ifpga_bs_wm_1)
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add r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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moveq pc, lr
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Lifpga_bs_wm_1_loop:
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ldrb r3, [r1], #1
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strb r3, [r0]
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subs r2, r2, #1
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bne Lifpga_bs_wm_1_loop
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mov pc, lr
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ENTRY(ifpga_bs_wm_2)
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add r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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moveq pc, lr
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Lifpga_bs_wm_2_loop:
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ldrh r3, [r1], #2
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strh r3, [r0]
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subs r2, r2, #1
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bne Lifpga_bs_wm_2_loop
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mov pc, lr
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ENTRY(ifpga_bs_wm_4)
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add r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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moveq pc, lr
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Lifpga_bs_wm_4_loop:
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ldr r3, [r1], #4
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str r3, [r0]
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subs r2, r2, #1
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bne Lifpga_bs_wm_4_loop
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mov pc, lr
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/*
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* read region
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*/
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ENTRY(ifpga_bs_rr_2)
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add r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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moveq pc, lr
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Lifpga_rr_2_loop:
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ldrh r3, [r0], #2
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strh r3, [r1], #2
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subs r2, r2, #1
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bne Lifpga_rr_2_loop
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mov pc, lr
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ENTRY(ifpga_bs_rr_4)
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add r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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moveq pc, lr
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Lifpga_rr_4_loop:
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ldr r3, [r0], #4
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str r3, [r1], #4
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subs r2, r2, #1
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bne Lifpga_rr_4_loop
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mov pc, lr
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/*
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* write region.
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*/
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ENTRY(ifpga_bs_wr_2)
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add r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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moveq pc, lr
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Lifpga_wr_2_loop:
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ldrh r3, [r1], #2
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strh r3, [r0], #2
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subs r2, r2, #1
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bne Lifpga_wr_2_loop
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mov pc, lr
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ENTRY(ifpga_bs_wr_4)
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add r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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moveq pc, lr
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Lifpga_wr_4_loop:
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ldr r3, [r1], #4
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str r3, [r0], #4
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subs r2, r2, #1
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bne Lifpga_wr_4_loop
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mov pc, lr
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/*
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* set region
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*/
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ENTRY(ifpga_bs_sr_2)
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add r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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moveq pc, lr
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Lifpga_bs_sr_2_loop:
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strh r1, [r0], #2
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subs r2, r2, #1
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bne Lifpga_bs_sr_2_loop
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mov pc, lr
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/*
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* copy region
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*/
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ENTRY(ifpga_bs_c_2)
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add r0, r1, r2
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ldr r2, [sp, #0]
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add r1, r2, r3
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ldr r2, [sp, #4]
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teq r2, #0
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moveq pc, lr
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cmp r0, r1
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blt Lifpga_bs_c_2_backwards
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Lifpga_bs_cf_2_loop:
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ldrh r3, [r0], #2
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strh r3, [r1], #2
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subs r2, r2, #1
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bne Lifpga_bs_cf_2_loop
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mov pc, lr
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Lifpga_bs_c_2_backwards:
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add r0, r0, r2, lsl #1
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add r1, r1, r2, lsl #1
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sub r0, r0, #2
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sub r1, r1, #2
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Lifpga_bs_cb_2_loop:
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ldrh r3, [r0], #-2
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strh r3, [r1], #-2
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subs r2, r2, #1
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bne Lifpga_bs_cb_2_loop
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mov pc, lr
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