330 lines
8.6 KiB
C
330 lines
8.6 KiB
C
/* $NetBSD: universe_pci.c,v 1.2 2000/03/12 11:21:02 drochner Exp $ */
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/*
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* Copyright (c) 1999
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* Matthias Drochner. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Common functions for PCI-VME-interfaces using the
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* Newbridge/Tundra Universe II chip (CA91C142).
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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/*#include <dev/pci/pcidevs.h>*/
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#include <machine/bus.h>
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#include <dev/vme/vmereg.h>
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#include <dev/vme/vmevar.h>
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#include <dev/ic/universereg.h>
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#include <dev/pci/universe_pci_var.h>
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int univ_pci_intr __P((void *));
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#define read_csr_4(d, reg) \
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bus_space_read_4(d->csrt, d->csrh, offsetof(struct universereg, reg))
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#define write_csr_4(d, reg, val) \
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bus_space_write_4(d->csrt, d->csrh, offsetof(struct universereg, reg), val)
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#define _pso(i) offsetof(struct universereg, __CONCAT(pcislv, i))
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static int pcislvoffsets[8] = {
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_pso(0), _pso(1), _pso(2), _pso(3),
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_pso(4), _pso(5), _pso(6), _pso(7)
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};
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#undef _pso
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#define read_pcislv(d, idx, reg) \
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bus_space_read_4(d->csrt, d->csrh, \
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pcislvoffsets[idx] + offsetof(struct universe_pcislvimg, reg))
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#define write_pcislv(d, idx, reg, val) \
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bus_space_write_4(d->csrt, d->csrh, \
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pcislvoffsets[idx] + offsetof(struct universe_pcislvimg, reg), val)
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#define _vso(i) offsetof(struct universereg, __CONCAT(vmeslv, i))
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static int vmeslvoffsets[8] = {
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_vso(0), _vso(1), _vso(2), _vso(3),
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_vso(4), _vso(5), _vso(6), _vso(7)
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};
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#undef _vso
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#define read_vmeslv(d, idx, reg) \
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bus_space_read_4(d->csrt, d->csrh, \
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vmeslvoffsets[idx] + offsetof(struct universe_vmeslvimg, reg))
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#define write_vmeslv(d, idx, reg, val) \
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bus_space_write_4(d->csrt, d->csrh, \
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vmeslvoffsets[idx] + offsetof(struct universe_vmeslvimg, reg), val)
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int
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univ_pci_attach(d, pa, name, inthdl, intcookie)
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struct univ_pci_data *d;
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struct pci_attach_args *pa;
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const char *name;
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void (*inthdl) __P((void *, int, int));
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void *intcookie;
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{
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pci_chipset_tag_t pc = pa->pa_pc;
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pci_intr_handle_t ih;
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const char *intrstr = NULL;
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u_int32_t reg;
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int i;
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d->pc = pc;
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strncpy(d->devname, name, sizeof(d->devname));
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d->devname[sizeof(d->devname) - 1] = '\0';
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if (pci_mapreg_map(pa, 0x10,
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PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
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0, &d->csrt, &d->csrh, NULL, NULL) &&
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pci_mapreg_map(pa, 0x14,
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PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
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0, &d->csrt, &d->csrh, NULL, NULL) &&
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pci_mapreg_map(pa, 0x10,
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PCI_MAPREG_TYPE_IO,
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0, &d->csrt, &d->csrh, NULL, NULL) &&
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pci_mapreg_map(pa, 0x14,
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PCI_MAPREG_TYPE_IO,
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0, &d->csrt, &d->csrh, NULL, NULL))
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return (-1);
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/* name sure the chip is in a sane state */
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write_csr_4(d, lint_en, 0); /* mask all PCI interrupts */
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write_csr_4(d, vint_en, 0); /* mask all VME interrupts */
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write_csr_4(d, dgcs, 0x40000000); /* stop DMA activity */
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for (i = 0; i < 8; i++) {
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univ_pci_unmapvme(d, i);
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univ_pci_unmappci(d, i);
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}
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write_csr_4(d, slsi, 0); /* disable "special PCI slave image" */
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/* enable DMA */
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pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
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pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) |
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PCI_COMMAND_MASTER_ENABLE);
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reg = read_csr_4(d, misc_ctl);
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printf("%s: ", name);
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if (reg & 0x00020000) /* SYSCON */
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printf("VME bus controller, ");
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reg = read_csr_4(d, mast_ctl);
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printf("requesting at VME bus level %d\n", (reg >> 22) & 3);
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/* Map and establish the PCI interrupt. */
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if (pci_intr_map(pc, pa->pa_intrtag, pa->pa_intrpin,
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pa->pa_intrline, &ih)) {
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printf("%s: couldn't map interrupt\n", name);
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return (-1);
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}
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intrstr = pci_intr_string(pc, ih);
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/*
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* Use a low interrupt level (the lowest?).
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* We will raise before calling a subdevice's handler.
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*/
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d->ih = pci_intr_establish(pc, ih, IPL_BIO, univ_pci_intr, d);
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if (d->ih == NULL) {
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printf("%s: couldn't establish interrupt", name);
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if (intrstr != NULL)
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printf(" at %s", intrstr);
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printf("\n");
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return (-1);
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}
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printf("%s: interrupting at %s\n", name, intrstr);
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/* handle all VME interrupts (XXX should be configurable) */
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d->vmeinthandler = inthdl;
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d->vmeintcookie = intcookie;
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write_csr_4(d, lint_stat, 0x00ff37ff); /* ack all pending IRQs */
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write_csr_4(d, lint_en, 0x000000fe); /* enable VME IRQ 1..7 */
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return (0);
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}
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int
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univ_pci_mapvme(d, wnd, vmebase, len, am, datawidth, pcibase)
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struct univ_pci_data *d;
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int wnd;
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vme_addr_t vmebase;
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u_int32_t len;
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vme_am_t am;
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vme_datasize_t datawidth;
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u_int32_t pcibase;
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{
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u_int32_t ctl = 0x80000000;
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switch (am & VME_AM_ADRSIZEMASK) {
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case VME_AM_A32:
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ctl |= 0x00020000;
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break;
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case VME_AM_A24:
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ctl |= 0x00010000;
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break;
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case VME_AM_A16:
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break;
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default:
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return (EINVAL);
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}
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if (am & VME_AM_SUPER)
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ctl |= 0x00001000;
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if ((am & VME_AM_MODEMASK) == VME_AM_PRG)
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ctl |= 0x00004000;
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if (datawidth & VME_D32)
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ctl |= 0x00800000;
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else if (datawidth & VME_D16)
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ctl |= 0x00400000;
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else if (!(datawidth & VME_D8))
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return (EINVAL);
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#ifdef UNIV_DEBUG
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printf("%s: wnd %d, map VME %x-%x to %x, ctl=%x\n",
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d->devname, wnd, vmebase, vmebase + len, pcibase, ctl);
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#endif
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write_pcislv(d, wnd, lsi_bs, pcibase);
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write_pcislv(d, wnd, lsi_bd, pcibase + len);
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write_pcislv(d, wnd, lsi_to, vmebase - pcibase);
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write_pcislv(d, wnd, lsi_ctl, ctl);
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return (0);
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}
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void
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univ_pci_unmapvme(d, wnd)
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struct univ_pci_data *d;
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int wnd;
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{
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#ifdef UNIV_DEBUG
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printf("%s: unmap VME wnd %d\n", d->devname, wnd);
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#endif
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write_pcislv(d, wnd, lsi_ctl, 0);
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}
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int
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univ_pci_mappci(d, wnd, pcibase, len, vmebase, am)
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struct univ_pci_data *d;
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int wnd;
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u_int32_t pcibase;
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u_int32_t len;
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vme_addr_t vmebase;
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vme_am_t am;
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{
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u_int32_t ctl = 0x80000000;
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switch (am & VME_AM_ADRSIZEMASK) {
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case VME_AM_A32:
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ctl |= 0x00020000;
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break;
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case VME_AM_A24:
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ctl |= 0x00010000;
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break;
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case VME_AM_A16:
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break;
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default:
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return (EINVAL);
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}
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if (am & VME_AM_SUPER)
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ctl |= 0x00200000;
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else
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ctl |= 0x00300000; /* both */
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if ((am & VME_AM_MODEMASK) == VME_AM_PRG)
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ctl |= 0x00800000;
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else
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ctl |= 0x00c00000; /* both */
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#ifdef UNIV_DEBUG
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printf("%s: wnd %d, map PCI %x-%x to %x, ctl=%x\n",
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d->devname, wnd, pcibase, pcibase + len, vmebase, ctl);
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#endif
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write_vmeslv(d, wnd, vsi_bs, vmebase);
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write_vmeslv(d, wnd, vsi_bd, vmebase + len);
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write_vmeslv(d, wnd, vsi_to, pcibase - vmebase);
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write_vmeslv(d, wnd, vsi_ctl, ctl);
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return (0);
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}
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void
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univ_pci_unmappci(d, wnd)
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struct univ_pci_data *d;
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int wnd;
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{
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#ifdef UNIV_DEBUG
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printf("%s: unmap PCI wnd %d\n", d->devname, wnd);
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#endif
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write_vmeslv(d, wnd, vsi_ctl, 0);
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}
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int
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univ_pci_vmebuserr(d, clear)
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struct univ_pci_data *d;
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int clear;
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{
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u_int32_t pcicsr;
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pcicsr = read_csr_4(d, pci_csr);
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if ((pcicsr & 0xf8000000) && clear)
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write_csr_4(d, pci_csr, pcicsr | 0xf8000000);
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return (pcicsr & 0x08000000); /* target abort */
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}
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int
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univ_pci_intr(v)
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void *v;
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{
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struct univ_pci_data *d = v;
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u_int32_t intcsr;
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int i, vec;
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intcsr = read_csr_4(d, lint_stat) & 0xffffff;
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if (!intcsr)
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return (0);
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/* ack everything */
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write_csr_4(d, lint_stat, intcsr);
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#ifdef UNIV_DEBUG
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printf("%s: intr, lint_stat=%x\n", d->devname, intcsr);
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#endif
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if (intcsr & 0x000000fe) { /* VME interrupt */
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for (i = 7; i >= 1; i--) {
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if (!(intcsr & (1 << i)))
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continue;
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vec = read_csr_4(d, v_statid[i - 1]);
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if (vec & 0x100) {
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printf("%s: err irq %d\n", d->devname, i);
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continue;
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}
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if (d->vmeinthandler)
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(*d->vmeinthandler)(d->vmeintcookie, i, vec);
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}
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}
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return (1);
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}
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