117 lines
4.7 KiB
C
117 lines
4.7 KiB
C
/* $NetBSD: rf3000reg.h,v 1.3 2004/07/21 04:25:22 dyoung Exp $ */
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/*
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* Copyright (c) 2005 David Young. All rights reserved.
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*
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* This code was written by David Young.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David
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* Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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#ifndef _DEV_IC_RF3000REG_H_
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#define _DEV_IC_RF3000REG_H_
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/*
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* Serial bus format for RF Microdevices RF3000 spread-spectrum
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* baseband modem.
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*/
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#define RF3000_TWI_DATA_MASK 0xff
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#define RF3000_TWI_ADDR_MASK 0x7f
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#define RF3000_TWI_AI 0x80 /* auto-increment */
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/*
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* Registers for RFMD RF3000.
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*/
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#define RF3000_CTL 0x01 /* modem control */
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#define RF3000_CTL_MODE_MASK BITS(7, 4)
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#define RF3000_CTL_MODE_1MBPS 0
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#define RF3000_CTL_MODE_RSVD0 1
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#define RF3000_CTL_MODE_2MBPS 2
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#define RF3000_CTL_MODE_2MBPS_SHORT 3
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#define RF3000_CTL_MODE_5MBPS 4
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#define RF3000_CTL_MODE_5MBPS_SHORT 5
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#define RF3000_CTL_MODE_11MBPS 6
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#define RF3000_CTL_MODE_11MBPS_SHORT 7
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#define RF3000_CTL_MODE_BPSK 8
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#define RF3000_CTL_MODE_QPSK 9
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#define RF3000_CTL_MODE_RSVD1 10
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#define RF3000_CTL_MODE_RSVD2 11
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#define RF3000_RXSTAT RF3000_CTL /* RX status */
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#define RF3000_RXSTAT_SHORTPRE BIT(3) /* 1: short preamble */
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#define RF3000_RXSTAT_ACQ BIT(2) /* 1: acquired */
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#define RF3000_RXSTAT_SFD BIT(1) /* 1: SFD detected */
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#define RF3000_RXSTAT_CRC BIT(0) /* 1: CRC invalid */
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#define RF3000_CCACTL 0x02 /* CCA control */
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/* CCA mode */
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#define RF3000_CCACTL_MODE_MASK BITS(7, 6)
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#define RF3000_CCACTL_MODE_RSSIT 0 /* RSSI threshold */
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#define RF3000_CCACTL_MODE_ACQ 1 /* acquisition */
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#define RF3000_CCACTL_MODE_BOTH 2 /* threshold or acq. */
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/* RSSI threshold for CCA */
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#define RF3000_CCACTL_RSSIT_MASK BITS(5, 0)
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#define RF3000_DIVCTL 0x03 /* diversity control */
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#define RF3000_DIVCTL_ENABLE BIT(7) /* enable diversity */
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#define RF3000_DIVCTL_ANTSEL BIT(6) /* if ENABLE = 0, set
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* ANT SEL
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*/
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#define RF3000_RSSI RF3000_DIVCTL /* RSSI value */
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#define RF3000_RSSI_MASK BITS(5, 0)
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#define RF3000_GAINCTL 0x11 /* TX variable gain control */
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#define RF3000_GAINCTL_TXVGC_MASK BITS(7, 2)
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#define RF3000_GAINCTL_SCRAMBLER BIT(1)
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#define RF3000_LOGAINCAL 0x14 /* low gain calibration */
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#define RF3000_LOGAINCAL_CAL_MASK BITS(5, 0)
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#define RF3000_HIGAINCAL 0x15 /* high gain calibration */
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#define RF3000_HIGAINCAL_CAL_MASK BITS(5, 0)
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#define RF3000_HIGAINCAL_DSSSPAD BIT(6) /* 6dB gain pad for DSSS
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* modes (meaning?)
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*/
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#define RF3000_OPTIONS1 0x1C /* Options Register 1 */
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/* Saturation threshold is 4 + offset, where -3 <= offset <= 3.
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* SAT_THRESH is the absolute value, SAT_THRESH_SIGN is the sign.
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*/
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#define RF3000_OPTIONS1_SAT_THRESH_SIGN BIT(7)
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#define RF3000_OPTIONS1_SAT_THRESH BITS(6,5)
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#define RF3000_OPTIONS1_ALTAGC BIT(4) /* 1: retrigger AGC
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* algorithm on ADC
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* saturation
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*/
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#define RF3000_OPTIONS1_ALTBUS BIT(3) /* 1: enable alternate
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* Tx/Rx data bus
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* interface.
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*/
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#define RF3000_OPTIONS1_RESERVED0_MASK BITS(2,0)/* 0 */
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#define RF3000_OPTIONS2 0x1D /* Options Register 2 */
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/* 1: delay next AGC 2us instead of 1us after a 1->0 LNAGS-pin transition. */
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#define RF3000_OPTIONS2_LNAGS_DELAY BIT(7)
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#define RF3000_OPTIONS2_RESERVED0_MASK BITS(6,3) /* 0 */
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/* Threshold for AGC re-trigger. 0: high count, 1: low count. */
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#define RF3000_OPTIONS2_RTG_THRESH BIT(2)
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#define RF3000_OPTIONS2_RESERVED1_MASK BITS(1,0) /* 0 */
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#endif /* _DEV_IC_RF3000REG_H_ */
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