102 lines
4.4 KiB
C
102 lines
4.4 KiB
C
/* $NetBSD: aupcireg.h,v 1.1 2006/02/09 00:26:40 gdamore Exp $ */
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/*-
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* Copyright (c) 2006 Itronix Inc.
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* All rights reserved.
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*
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* Written by Garrett D'Amore for Itronix Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of Itronix Inc. may not be used to endorse
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* or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MIPS_ALCHEMY_DEV_AUPCIREG_H
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#define _MIPS_ALCHEMY_DEV_AUPCIREG_H
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#define AUPCI_CMEM 0x0000
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#define AUPCI_CMEM_HC (1UL<<31) /* host config */
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#define AUPCI_CMEM_E (1UL<<28) /* cmem enable */
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#define AUPCI_CONFIG 0x0004
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#define AUPCI_CONFIG_EADDRH_SHIFT 28 /* bits 32-35 */
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#define AUPCI_CONFIG_ERD (1UL<<27) /* error direction */
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#define AUPCI_CONFIG_ET (1UL<<26) /* error target */
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#define AUPCI_CONFIG_EF (1UL<<25) /* fatal error */
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#define AUPCI_CONFIG_EP (1UL<<24) /* parity error */
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#define AUPCI_CONFIG_EM (1UL<<23) /* multiple errors */
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#define AUPCI_CONfIG_BM (1UL<<22) /* bad master */
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#define AUPCI_CONFIG_PD (1UL<<20) /* PCI disable */
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#define AUPCI_CONFIG_BME (1UL<<19) /* byte mask enable */
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#define AUPCI_CONFIG_DR (1UL<<18) /* drive mode */
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#define AUPCI_CONFIG_NC (1UL<<16) /* non-coherent */
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#define AUPCI_CONFIG_IE (1UL<<15) /* interrupt enable */
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#define AUPCI_CONFIG_IP (1UL<<13) /* perr int enable */
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#define AUPCI_CONFIG_IS (1UL<<12) /* serr int enable */
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#define AUPCI_CONFIG_IMM (1UL<<11) /* master abort int */
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#define AUPCI_CONFIG_ITM (1UL<<10) /* target abort int */
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#define AUPCI_CONFIG_ITT (1UL<<9) /* target abort int */
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#define AUPCI_CONFIG_IPB (1UL<<8) /* perr rec int */
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#define AUPCI_CONFIG_SIC_SHIFT 6
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#define AUPCI_CONFIG_SIC_NONE 0
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#define AUPCI_CONFIG_SIC_ADDR (1UL<<6)
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#define AUPCI_CONFIG_SIC_DATA (2UL<<6)
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#define AUPCI_CONFIG_SIC_ALL (3UL<<6)
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#define AUPCI_CONFIG_SIC_MASK (3UL<<6)
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#define AUPCI_CONFIG_ST (1UL<<5) /* swap on target */
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#define AUPCI_CONFIG_SM (1UL<<4) /* swap on master */
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#define AUPCI_CONFIG_AEN (1UL<<3) /* enable arbiter */
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#define AUPCI_CONFIG_R2H (1UL<<2) /* req 2 high pri */
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#define AUPCI_CONFIG_R1H (1UL<<1) /* req 1 high pri */
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#define AUPCI_CONFIG_CH (1UL<<0) /* cpu high pri */
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#define AUPCI_B2BMASK 0x0008
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#define AUPCI_B2BMASK_SHIFT 16
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#define AUPCI_B2BBASE0 0x000C
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#define AUPCI_B2BASE0_SHIFT 16
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#define AUPCI_B2BBASE1 0x0010
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#define AUPCI_B2BASE1_SHIFT 16
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#define AUPCI_MWMASK 0x0014
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#define AUPCI_MWMASK_SHIFT 16
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#define AUPCI_MWBASE 0x0018
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#define AUPCI_MWBASE_SHIFT 16
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#define AUPCI_ERRADDR 0x001C
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#define AUPCI_SPECINTACK 0x0020
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#define AUPCI_PRCFG 0x0024
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#define AUPCI_PRCFG_BLM_SHIFT 3
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#define AUPCI_PRCFG_AM (1UL<<9) /* abort mask */
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#define AUPCI_PRCFG_DM (1UL<<8) /* done mask */
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#define AUPCI_PRCFG_BS_SHIFT 4
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#define AUPCI_PRCFG_ADDR_HIGH_SHIFT 0
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#define AUPCI_PRADDR 0x0028
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#define AUPCI_PRSTAT 0x002C
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#define AUPCI_PRSTAT_AI (1UL<<9) /* posted read abort */
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#define AUPCI_PRSTAT_DI (1UL<<8) /* posted read done */
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#define AUPCI_PRSTAT_PEND (1UL<<0) /* posted read pend */
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#define AUPCI_ID 0x0100
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#define AUPCI_COMMAND_STATUS 0x0104
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#define AUPCI_CLASS 0x0108
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#endif /* _MIPS_ALCHEMY_DEV_AUPCIREG_H */
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