59474a8c82
SH-5, meet NetBSD. Let's hope this is the start of a long and fruitful relationship. :-) This code, funded by Wasabi Systems, adds initial support for the Hitachi SuperH(tm) SH-5 cpu architecture to NetBSD. At the present time, NetBSD/evbsh5 only runs on a SH-5 core simulator which has no simulated devices other than a simple console. However, it is good enough to get to the "root device: " prompt. Device driver support for Real SH-5 Hardware is in place, particularly for supporting the up-coming Cayman evaluation board, and should be quite easy to get running when the hardware is available. There is no in-tree toolchain for this port at this time. Gcc-current has rudimentary SH-5 support but it is known to be buggy. A working toolchain was obtained from SuperH to facilitate this port. Gcc-current will be fixed in due course. The SH-5 architecture is fully 64-bit capable, although NetBSD/evbsh5 has currently only been tested in 32-bit mode. It is bi-endian, via a boot- time option and it also has an "SHcompact" mode in which it will execute SH-[34] user-land instructions. For more information on the SH-5, see www.superh.com. Suffice to say it is *not* just another respin of the SH-[34].
96 lines
4.1 KiB
C
96 lines
4.1 KiB
C
/* $NetBSD: cprcreg.h,v 1.1 2002/07/05 13:31:51 scw Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Steve C. Woodford for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SH5_CPRCREG_H
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#define _SH5_CPRCREG_H
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/*
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* Register Offsets for the Clock, Power, Watchdog and Reset Controller Module
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*/
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#define CPRC_REG_FRQ 0x00 /* Clock: Frequency Control Register */
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#define CPRC_REG_PLL 0x08 /* Clock: PLL1 Control Register */
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#define CPRC_REG_WTCNT 0x10 /* Watchdog: Count Register */
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#define CPRC_REG_WTCS 0x18 /* Watchdog: Control/Status Register */
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#define CPRC_REG_MSTP 0x20 /* Power: Module Stop Register */
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#define CPRC_REG_MSTPACK 0x28 /* Power: Module Stop Ack Register */
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#define CPRC_REG_STBCR 0x30 /* Power: Control Register */
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#define CPRC_REG_RST 0x38 /* Reset: Control Register */
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#define CPRC_REG_SIZE 0x40
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/*
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* Bit definitions for CPRC_REG_FRQ
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*/
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#define CPRC_FRQ_MASK 0x07 /* Mask for clock divider fields */
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#define CPRC_FRQ_EMC_SHIFT 0 /* External Memory Clk Divider Ratio */
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#define CPRC_FRQ_BMC_SHIFT 3 /* SuperHyway Clock Divider Ratio */
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#define CPRC_FRQ_IFC_SHIFT 6 /* CPU Clock Divider Ratio */
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#define CPRC_FRQ_PBC_SHIFT 12 /* Peripheral Clock Divider Ratio */
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#define CPRC_FRQ_PCC_SHIFT 15 /* PCIbus Clock Divider Ratio */
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#define CPRC_FRQ_FMC_SHIFT 18 /* Flash Memory I/F Clk Divider Ratio */
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#define CPRC_FRQ_SBC_SHIFT 21 /* ST Legacy Bus Clock Divider Ratio */
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#define CPRC_FRQ_PLL2EN 0x0200 /* PLL2 Enable (PLL2 not in eval) */
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#define CPRC_FRQ_PLL1EN 0x0400 /* PLL1 Enable */
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#define CPRC_FRQ_CKOEN 0x0800 /* Clock output enable (Not in eval) */
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/*
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* Given an encoded divider ratio from the CPRC_REG_FRQ register, this
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* macro evaluates to "1/actual ratio" it represents.
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*
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* So, the encoding "0" represents the ratio 1/2. In this case,
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* the macro evaluates to "2".
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*/
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#define CPRC_FRQ2DIV(f) (((f)<6)?(((f)+1)*2):(((f)==6)?16:24))
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/*
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* Bit definitions for CPRC_REG_PLL
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*/
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#define CPRC_PLL_MDIV_MASK 0xff /* PLL1 Pre-divider */
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#define CPRC_PLL_MDIV_SHIFT 0
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#define CPRC_PLL_NDIV_MASK 0xff /* PLL1 Feedback divider */
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#define CPRC_PLL_NDIV_SHIFT 8
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#define CPRC_PLL_PDIV_MASK 0x07 /* PLL1 Post divider */
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#define CPRC_PLL_PDIV_SHIFT 16
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#define CPRC_PLL_SETUP_MASK 0x1ff /* PLL1 Loop characteristics */
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#define CPRC_PLL_SETUP_SHIFT 19
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#define CPRC_PLL_ENABLE_MASK 0x03 /* PLL1 Enabling Truth Table */
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#define CPRC_PLL_ENABLE_SHIFT 28
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#define CPRC_PLL_LOCKED (1<<30) /* PLL1 Locked */
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#define CPRC_PLL_POWER (1<<31) /* PLL1 Power Control */
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#endif /* _SH5_CPRCREG_H */
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