828 lines
32 KiB
C
828 lines
32 KiB
C
/* $NetBSD: bus.h,v 1.15 2005/12/11 12:18:43 christos Exp $ */
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/* $OpenBSD: bus.h,v 1.1 1997/10/13 10:53:42 pefo Exp $ */
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/*-
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* Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1996 Charles M. Hannum. All rights reserved.
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* Copyright (c) 1996 Jason R. Thorpe. All rights reserved.
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* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Christopher G. Demetriou
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* for the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1997 Per Fogelstrom. All rights reserved.
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* Copyright (c) 1996 Niklas Hallqvist. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Christopher G. Demetriou
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* for the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _POWERPC_BUS_H_
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#define _POWERPC_BUS_H_
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#if defined(_KERNEL_OPT) && !defined(BUS_DMA_COHERENT)
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#include "opt_ppcarch.h"
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#if defined(PPC_IBM4XX)
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#define BUS_DMA_COHERENT BUS_DMA_NOCACHE
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#endif /* PPC_IBM4XX */
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#endif /* _KERNEL_OPT && !BUS_DMA_COHERENT */
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/*
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* Bus access types.
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*/
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typedef u_int32_t bus_addr_t;
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typedef u_int32_t bus_size_t;
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typedef u_int32_t bus_space_handle_t;
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typedef const struct powerpc_bus_space *bus_space_tag_t;
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struct extent;
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struct powerpc_bus_space_scalar {
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u_int8_t (*pbss_read_1)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t);
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u_int16_t (*pbss_read_2)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t);
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u_int32_t (*pbss_read_4)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t);
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u_int64_t (*pbss_read_8)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t);
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void (*pbss_write_1)(bus_space_tag_t, bus_space_handle_t, bus_size_t,
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u_int8_t);
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void (*pbss_write_2)(bus_space_tag_t, bus_space_handle_t, bus_size_t,
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u_int16_t);
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void (*pbss_write_4)(bus_space_tag_t, bus_space_handle_t, bus_size_t,
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u_int32_t);
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void (*pbss_write_8)(bus_space_tag_t, bus_space_handle_t, bus_size_t,
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u_int64_t);
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};
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struct powerpc_bus_space_group {
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void (*pbsg_read_1)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, u_int8_t *, size_t);
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void (*pbsg_read_2)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, u_int16_t *, size_t);
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void (*pbsg_read_4)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, u_int32_t *, size_t);
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void (*pbsg_read_8)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, u_int64_t *, size_t);
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void (*pbsg_write_1)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, const u_int8_t *, size_t);
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void (*pbsg_write_2)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, const u_int16_t *, size_t);
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void (*pbsg_write_4)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, const u_int32_t *, size_t);
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void (*pbsg_write_8)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, const u_int64_t *, size_t);
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};
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struct powerpc_bus_space_set {
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void (*pbss_set_1)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, u_int8_t, size_t);
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void (*pbss_set_2)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, u_int16_t, size_t);
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void (*pbss_set_4)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, u_int32_t, size_t);
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void (*pbss_set_8)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, u_int64_t, size_t);
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};
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struct powerpc_bus_space_copy {
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void (*pbsc_copy_1)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, bus_space_handle_t, bus_size_t, size_t);
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void (*pbsc_copy_2)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, bus_space_handle_t, bus_size_t, size_t);
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void (*pbsc_copy_4)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, bus_space_handle_t, bus_size_t, size_t);
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void (*pbsc_copy_8)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, bus_space_handle_t, bus_size_t, size_t);
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};
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struct powerpc_bus_space {
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int pbs_flags;
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#define _BUS_SPACE_BIG_ENDIAN 0x00000100
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#define _BUS_SPACE_LITTLE_ENDIAN 0x00000000
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#define _BUS_SPACE_IO_TYPE 0x00000200
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#define _BUS_SPACE_MEM_TYPE 0x00000000
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#define _BUS_SPACE_STRIDE_MASK 0x0000001f
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bus_addr_t pbs_offset; /* offset to real start */
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bus_addr_t pbs_base; /* extent base */
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bus_addr_t pbs_limit; /* extent limit */
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struct extent *pbs_extent;
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paddr_t (*pbs_mmap)(bus_space_tag_t, bus_addr_t, off_t, int, int);
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int (*pbs_map)(bus_space_tag_t, bus_addr_t, bus_size_t, int,
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bus_space_handle_t *);
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void (*pbs_unmap)(bus_space_tag_t, bus_space_handle_t, bus_size_t);
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int (*pbs_alloc)(bus_space_tag_t, bus_addr_t, bus_addr_t, bus_size_t,
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bus_size_t align, bus_size_t, int, bus_addr_t *,
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bus_space_handle_t *);
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void (*pbs_free)(bus_space_tag_t, bus_space_handle_t, bus_size_t);
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int (*pbs_subregion)(bus_space_tag_t, bus_space_handle_t, bus_size_t,
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bus_size_t, bus_space_handle_t *);
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struct powerpc_bus_space_scalar pbs_scalar;
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struct powerpc_bus_space_scalar pbs_scalar_stream;
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const struct powerpc_bus_space_group *pbs_multi;
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const struct powerpc_bus_space_group *pbs_multi_stream;
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const struct powerpc_bus_space_group *pbs_region;
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const struct powerpc_bus_space_group *pbs_region_stream;
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const struct powerpc_bus_space_set *pbs_set;
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const struct powerpc_bus_space_set *pbs_set_stream;
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const struct powerpc_bus_space_copy *pbs_copy;
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};
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#define _BUS_SPACE_STRIDE(t, o) \
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((o) << ((t)->pbs_flags & _BUS_SPACE_STRIDE_MASK))
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#define _BUS_SPACE_UNSTRIDE(t, o) \
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((o) >> ((t)->pbs_flags & _BUS_SPACE_STRIDE_MASK))
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#define BUS_SPACE_MAP_CACHEABLE 0x01
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#define BUS_SPACE_MAP_LINEAR 0x02
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#define BUS_SPACE_MAP_PREFETCHABLE 0x04
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#ifdef __STDC__
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#define CAT(a,b) a##b
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#define CAT3(a,b,c) a##b##c
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#else
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#define CAT(a,b) a/**/b
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#define CAT3(a,b,c) a/**/b/**/c
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#endif
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int bus_space_init(struct powerpc_bus_space *, const char *, caddr_t, size_t);
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void bus_space_mallocok(void);
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/*
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* Access methods for bus resources
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*/
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#define __BUS_SPACE_HAS_STREAM_METHODS
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/*
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* void *bus_space_vaddr (bus_space_tag_t, bus_space_handle_t);
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*
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* Get the kernel virtual address for the mapped bus space.
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* Only allowed for regions mapped with BUS_SPACE_MAP_LINEAR.
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* (XXX not enforced)
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*/
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#define bus_space_vaddr(t, h) ((void *)(h))
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/*
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* paddr_t bus_space_mmap (bus_space_tag_t t, bus_addr_t addr,
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* off_t offset, int prot, int flags);
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*
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* Mmap a region of bus space.
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*/
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#define bus_space_mmap(t, b, o, p, f) \
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((*(t)->pbs_mmap)((t), (b), (o), (p), (f)))
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/*
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* int bus_space_map (bus_space_tag_t t, bus_addr_t addr,
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* bus_size_t size, int flags, bus_space_handle_t *bshp);
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*
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* Map a region of bus space.
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*/
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#define bus_space_map(t, a, s, f, hp) \
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((*(t)->pbs_map)((t), (a), (s), (f), (hp)))
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/*
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* int bus_space_unmap (bus_space_tag_t t,
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* bus_space_handle_t bsh, bus_size_t size);
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*
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* Unmap a region of bus space.
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*/
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#define bus_space_unmap(t, h, s) \
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((void)(*(t)->pbs_unmap)((t), (h), (s)))
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/*
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* int bus_space_subregion (bus_space_tag_t t,
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* bus_space_handle_t bsh, bus_size_t offset, bus_size_t size,
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* bus_space_handle_t *nbshp);
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*
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* Get a new handle for a subregion of an already-mapped area of bus space.
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*/
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#define bus_space_subregion(t, h, o, s, hp) \
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((*(t)->pbs_subregion)((t), (h), (o), (s), (hp)))
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/*
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* int bus_space_alloc (bus_space_tag_t t, bus_addr_t rstart,
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* bus_addr_t rend, bus_size_t size, bus_size_t align,
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* bus_size_t boundary, int flags, bus_addr_t *bpap,
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* bus_space_handle_t *bshp);
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*
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* Allocate a region of bus space.
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*/
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#define bus_space_alloc(t, rs, re, s, a, b, f, ap, hp) \
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((*(t)->pbs_alloc)((t), (rs), (re), (s), (a), (b), (f), (ap), (hp)))
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/*
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* int bus_space_free (bus_space_tag_t t,
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* bus_space_handle_t bsh, bus_size_t size);
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*
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* Free a region of bus space.
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*/
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#define bus_space_free(t, h, s) \
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((void)(*(t)->pbs_free)((t), (h), (s)))
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/*
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* u_intN_t bus_space_read_N (bus_space_tag_t tag,
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* bus_space_handle_t bsh, bus_size_t offset);
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*
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* Read a 1, 2, 4, or 8 byte quantity from bus space
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* described by tag/handle/offset.
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*/
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#define bus_space_read_1(t, h, o) \
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((*(t)->pbs_scalar.pbss_read_1)((t), (h), (o)))
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#define bus_space_read_2(t, h, o) \
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((*(t)->pbs_scalar.pbss_read_2)((t), (h), (o)))
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#define bus_space_read_4(t, h, o) \
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((*(t)->pbs_scalar.pbss_read_4)((t), (h), (o)))
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#define bus_space_read_8(t, h, o) \
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((*(t)->pbs_scalar.pbss_read_8)((t), (h), (o)))
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/*
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* u_intN_t bus_space_read_stream_N (bus_space_tag_t tag,
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* bus_space_handle_t bsh, bus_size_t offset);
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*
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* Read a 2, 4, or 8 byte quantity from bus space
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* described by tag/handle/offset ignoring endianness.
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*/
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#define bus_space_read_stream_2(t, h, o) \
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((*(t)->pbs_scalar_stream.pbss_read_2)((t), (h), (o)))
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#define bus_space_read_stream_4(t, h, o) \
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((*(t)->pbs_scalar_stream.pbss_read_4)((t), (h), (o)))
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#define bus_space_read_stream_8(t, h, o) \
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((*(t)->pbs_scalar_stream.pbss_read_8)((t), (h), (o)))
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/*
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* void bus_space_read_multi_N _P((bus_space_tag_t tag,
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* bus_space_handle_t bsh, bus_size_t offset,
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* u_intN_t *addr, size_t count);
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*
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* Read `count' 1, 2, 4, or 8 byte quantities from bus space
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* described by tag/handle/offset and copy into buffer provided.
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*/
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#define bus_space_read_multi_1(t, h, o, a, c) \
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((*(t)->pbs_multi->pbsg_read_1)((t), (h), (o), (a), (c)))
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#define bus_space_read_multi_2(t, h, o, a, c) \
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((*(t)->pbs_multi->pbsg_read_2)((t), (h), (o), (a), (c)))
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#define bus_space_read_multi_4(t, h, o, a, c) \
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((*(t)->pbs_multi->pbsg_read_4)((t), (h), (o), (a), (c)))
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#define bus_space_read_multi_8(t, h, o, a, c) \
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((*(t)->pbs_multi->pbsg_read_8)((t), (h), (o), (a), (c)))
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/*
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* void bus_space_read_multi_stream_N (bus_space_tag_t tag,
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* bus_space_handle_t bsh, bus_size_t offset,
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* u_intN_t *addr, size_t count);
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*
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* Read `count' 2, 4, or 8 byte stream quantities from bus space
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* described by tag/handle/offset and copy into buffer provided.
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*/
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#define bus_space_read_multi_stream_2(t, h, o, a, c) \
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((*(t)->pbs_multi_stream->pbsg_read_2)((t), (h), (o), (a), (c)))
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#define bus_space_read_multi_stream_4(t, h, o, a, c) \
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((*(t)->pbs_multi_stream->pbsg_read_4)((t), (h), (o), (a), (c)))
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#define bus_space_read_multi_stream_8(t, h, o, a, c) \
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((*(t)->pbs_multi_stream->pbsg_read_8)((t), (h), (o), (a), (c)))
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/*
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* void bus_space_write_N (bus_space_tag_t tag,
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* bus_space_handle_t bsh, bus_size_t offset,
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* u_intN_t value);
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*
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* Write the 1, 2, 4, or 8 byte value `value' to bus space
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* described by tag/handle/offset.
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*/
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#define bus_space_write_1(t, h, o, v) \
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((*(t)->pbs_scalar.pbss_write_1)((t), (h), (o), (v)))
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#define bus_space_write_2(t, h, o, v) \
|
|
((*(t)->pbs_scalar.pbss_write_2)((t), (h), (o), (v)))
|
|
#define bus_space_write_4(t, h, o, v) \
|
|
((*(t)->pbs_scalar.pbss_write_4)((t), (h), (o), (v)))
|
|
#define bus_space_write_8(t, h, o, v) \
|
|
((*(t)->pbs_scalar.pbss_write_8)((t), (h), (o), (v)))
|
|
|
|
/*
|
|
* void bus_space_write_stream_N (bus_space_tag_t tag,
|
|
* bus_space_handle_t bsh, bus_size_t offset,
|
|
* u_intN_t value);
|
|
*
|
|
* Write the 2, 4, or 8 byte stream value `value' to bus space
|
|
* described by tag/handle/offset.
|
|
*/
|
|
|
|
#define bus_space_write_stream_1(t, h, o, v) \
|
|
((*(t)->pbs_scalar_stream.pbss_write_1)((t), (h), (o), (v)))
|
|
#define bus_space_write_stream_2(t, h, o, v) \
|
|
((*(t)->pbs_scalar_stream.pbss_write_2)((t), (h), (o), (v)))
|
|
#define bus_space_write_stream_4(t, h, o, v) \
|
|
((*(t)->pbs_scalar_stream.pbss_write_4)((t), (h), (o), (v)))
|
|
#define bus_space_write_stream_8(t, h, o, v) \
|
|
((*(t)->pbs_scalar_stream.pbss_write_8)((t), (h), (o), (v)))
|
|
|
|
/*
|
|
* void bus_space_write_multi_N (bus_space_tag_t tag,
|
|
* bus_space_handle_t bsh, bus_size_t offset,
|
|
* const u_intN_t *addr, size_t count);
|
|
*
|
|
* Write `count' 1, 2, 4, or 8 byte quantities from the buffer
|
|
* provided to bus space described by tag/handle/offset.
|
|
*/
|
|
|
|
#define bus_space_write_multi_1(t, h, o, a, c) \
|
|
((*(t)->pbs_multi->pbsg_write_1)((t), (h), (o), (a), (c)))
|
|
#define bus_space_write_multi_2(t, h, o, a, c) \
|
|
((*(t)->pbs_multi->pbsg_write_2)((t), (h), (o), (a), (c)))
|
|
#define bus_space_write_multi_4(t, h, o, a, c) \
|
|
((*(t)->pbs_multi->pbsg_write_4)((t), (h), (o), (a), (c)))
|
|
#define bus_space_write_multi_8(t, h, o, a, c) \
|
|
((*(t)->pbs_multi->pbsg_write_8)((t), (h), (o), (a), (c)))
|
|
|
|
/*
|
|
* void bus_space_write_multi_stream_N (bus_space_tag_t tag,
|
|
* bus_space_handle_t bsh, bus_size_t offset,
|
|
* const u_intN_t *addr, size_t count);
|
|
*
|
|
* Write `count' 2, 4, or 8 byte stream quantities from the buffer
|
|
* provided to bus space described by tag/handle/offset.
|
|
*/
|
|
|
|
#define bus_space_write_multi_stream_1(t, h, o, a, c) \
|
|
((*(t)->pbs_multi_stream->pbsg_write_1)((t), (h), (o), (a), (c)))
|
|
#define bus_space_write_multi_stream_2(t, h, o, a, c) \
|
|
((*(t)->pbs_multi_stream->pbsg_write_2)((t), (h), (o), (a), (c)))
|
|
#define bus_space_write_multi_stream_4(t, h, o, a, c) \
|
|
((*(t)->pbs_multi_stream->pbsg_write_4)((t), (h), (o), (a), (c)))
|
|
#define bus_space_write_multi_stream_8(t, h, o, a, c) \
|
|
((*(t)->pbs_multi_stream->pbsg_write_8)((t), (h), (o), (a), (c)))
|
|
|
|
/*
|
|
* void bus_space_read_region_N (bus_space_tag_t tag,
|
|
* bus_space_handle_t bsh, bus_size_t offset,
|
|
* u_intN_t *addr, size_t count);
|
|
*
|
|
* Read `count' 1, 2, 4, or 8 byte quantities from bus space
|
|
* described by tag/handle and starting at `offset' and copy into
|
|
* buffer provided.
|
|
*/
|
|
#define bus_space_read_region_1(t, h, o, a, c) \
|
|
((*(t)->pbs_region->pbsg_read_1)((t), (h), (o), (a), (c)))
|
|
#define bus_space_read_region_2(t, h, o, a, c) \
|
|
((*(t)->pbs_region->pbsg_read_2)((t), (h), (o), (a), (c)))
|
|
#define bus_space_read_region_4(t, h, o, a, c) \
|
|
((*(t)->pbs_region->pbsg_read_4)((t), (h), (o), (a), (c)))
|
|
#define bus_space_read_region_8(t, h, o, a, c) \
|
|
((*(t)->pbs_region->pbsg_read_8)((t), (h), (o), (a), (c)))
|
|
|
|
/*
|
|
* void bus_space_read_region_stream_N (bus_space_tag_t tag,
|
|
* bus_space_handle_t bsh, bus_size_t offset,
|
|
* u_intN_t *addr, size_t count);
|
|
*
|
|
* Read `count' 2, 4, or 8 byte stream quantities from bus space
|
|
* described by tag/handle and starting at `offset' and copy into
|
|
* buffer provided.
|
|
*/
|
|
#define bus_space_read_region_stream_2(t, h, o, a, c) \
|
|
((*(t)->pbs_region_stream->pbsg_read_2)((t), (h), (o), (a), (c)))
|
|
#define bus_space_read_region_stream_4(t, h, o, a, c) \
|
|
((*(t)->pbs_region_stream->pbsg_read_4)((t), (h), (o), (a), (c)))
|
|
#define bus_space_read_region_stream_8(t, h, o, a, c) \
|
|
((*(t)->pbs_region_stream->pbsg_read_8)((t), (h), (o), (a), (c)))
|
|
|
|
/*
|
|
* void bus_space_write_region_N (bus_space_tag_t tag,
|
|
* bus_space_handle_t bsh, bus_size_t offset,
|
|
* const u_intN_t *addr, size_t count);
|
|
*
|
|
* Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided
|
|
* to bus space described by tag/handle starting at `offset'.
|
|
*/
|
|
#define bus_space_write_region_1(t, h, o, a, c) \
|
|
((*(t)->pbs_region->pbsg_write_1)((t), (h), (o), (a), (c)))
|
|
#define bus_space_write_region_2(t, h, o, a, c) \
|
|
((*(t)->pbs_region->pbsg_write_2)((t), (h), (o), (a), (c)))
|
|
#define bus_space_write_region_4(t, h, o, a, c) \
|
|
((*(t)->pbs_region->pbsg_write_4)((t), (h), (o), (a), (c)))
|
|
#define bus_space_write_region_8(t, h, o, a, c) \
|
|
((*(t)->pbs_region->pbsg_write_8)((t), (h), (o), (a), (c)))
|
|
|
|
/*
|
|
* void bus_space_write_region_stream_N (bus_space_tag_t tag,
|
|
* bus_space_handle_t bsh, bus_size_t offset,
|
|
* const u_intN_t *addr, size_t count);
|
|
*
|
|
* Write `count' 2, 4, or 8 byte stream quantities from the buffer provided
|
|
* to bus space described by tag/handle starting at `offset'.
|
|
*/
|
|
#define bus_space_write_region_stream_2(t, h, o, a, c) \
|
|
((*(t)->pbs_region_stream->pbsg_write_2)((t), (h), (o), (a), (c)))
|
|
#define bus_space_write_region_stream_4(t, h, o, a, c) \
|
|
((*(t)->pbs_region_stream->pbsg_write_4)((t), (h), (o), (a), (c)))
|
|
#define bus_space_write_region_stream_8(t, h, o, a, c) \
|
|
((*(t)->pbs_region_stream->pbsg_write_8)((t), (h), (o), (a), (c)))
|
|
|
|
#if 0
|
|
/*
|
|
* void bus_space_set_multi_N (bus_space_tag_t tag,
|
|
* bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
|
|
* size_t count);
|
|
*
|
|
* Write the 1, 2, 4, or 8 byte value `val' to bus space described
|
|
* by tag/handle/offset `count' times.
|
|
*/
|
|
#define bus_space_set_multi_1(t, h, o, v, c)
|
|
((*(t)->pbs_set_multi_1)((t), (h), (o), (v), (c)))
|
|
#define bus_space_set_multi_2(t, h, o, v, c)
|
|
((*(t)->pbs_set_multi_2)((t), (h), (o), (v), (c)))
|
|
#define bus_space_set_multi_4(t, h, o, v, c)
|
|
((*(t)->pbs_set_multi_4)((t), (h), (o), (v), (c)))
|
|
#define bus_space_set_multi_8(t, h, o, v, c)
|
|
((*(t)->pbs_set_multi_8)((t), (h), (o), (v), (c)))
|
|
|
|
/*
|
|
* void bus_space_set_multi_stream_N (bus_space_tag_t tag,
|
|
* bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
|
|
* size_t count);
|
|
*
|
|
* Write the 2, 4, or 8 byte stream value `val' to bus space described
|
|
* by tag/handle/offset `count' times.
|
|
*/
|
|
#define bus_space_set_multi_stream_2(t, h, o, v, c)
|
|
((*(t)->pbs_set_multi_stream_2)((t), (h), (o), (v), (c)))
|
|
#define bus_space_set_multi_stream_4(t, h, o, v, c)
|
|
((*(t)->pbs_set_multi_stream_4)((t), (h), (o), (v), (c)))
|
|
#define bus_space_set_multi_stream_8(t, h, o, v, c)
|
|
((*(t)->pbs_set_multi_stream_8)((t), (h), (o), (v), (c)))
|
|
|
|
#endif
|
|
|
|
/*
|
|
* void bus_space_set_region_N (bus_space_tag_t tag,
|
|
* bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
|
|
* size_t count);
|
|
*
|
|
* Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
|
|
* by tag/handle starting at `offset'.
|
|
*/
|
|
#define bus_space_set_region_1(t, h, o, v, c) \
|
|
((*(t)->pbs_set->pbss_set_1)((t), (h), (o), (v), (c)))
|
|
#define bus_space_set_region_2(t, h, o, v, c) \
|
|
((*(t)->pbs_set->pbss_set_2)((t), (h), (o), (v), (c)))
|
|
#define bus_space_set_region_4(t, h, o, v, c) \
|
|
((*(t)->pbs_set->pbss_set_4)((t), (h), (o), (v), (c)))
|
|
#define bus_space_set_region_8(t, h, o, v, c) \
|
|
((*(t)->pbs_set->pbss_set_8)((t), (h), (o), (v), (c)))
|
|
|
|
/*
|
|
* void bus_space_set_region_stream_N (bus_space_tag_t tag,
|
|
* bus_space_handle_t bsh, bus_size_t offset, u_intN_t val,
|
|
* size_t count);
|
|
*
|
|
* Write `count' 2, 4, or 8 byte stream value `val' to bus space described
|
|
* by tag/handle starting at `offset'.
|
|
*/
|
|
#define bus_space_set_region_stream_2(t, h, o, v, c) \
|
|
((*(t)->pbs_set_stream->pbss_set_2)((t), (h), (o), (v), (c)))
|
|
#define bus_space_set_region_stream_4(t, h, o, v, c) \
|
|
((*(t)->pbs_set_stream->pbss_set_4)((t), (h), (o), (v), (c)))
|
|
#define bus_space_set_region_stream_8(t, h, o, v, c) \
|
|
((*(t)->pbs_set_stream->pbss_set_8)((t), (h), (o), (v), (c)))
|
|
|
|
|
|
/*
|
|
* void bus_space_copy_region_N (bus_space_tag_t tag,
|
|
* bus_space_handle_t bsh1, bus_size_t off1,
|
|
* bus_space_handle_t bsh2, bus_size_t off2,
|
|
* size_t count);
|
|
*
|
|
* Copy `count' 1, 2, 4, or 8 byte values from bus space starting
|
|
* at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
|
|
*/
|
|
#define bus_space_copy_region_1(t, h1, o1, h2, o2, c) \
|
|
((*(t)->pbs_copy->pbsc_copy_1)((t), (h1), (o1), (h2), (o2), (c)))
|
|
#define bus_space_copy_region_2(t, h1, o1, h2, o2, c) \
|
|
((*(t)->pbs_copy->pbsc_copy_2)((t), (h1), (o1), (h2), (o2), (c)))
|
|
#define bus_space_copy_region_4(t, h1, o1, h2, o2, c) \
|
|
((*(t)->pbs_copy->pbsc_copy_4)((t), (h1), (o1), (h2), (o2), (c)))
|
|
#define bus_space_copy_region_8(t, h1, o1, h2, o2, c) \
|
|
((*(t)->pbs_copy->pbsc_copy_8)((t), (h1), (o1), (h2), (o2), (c)))
|
|
|
|
/*
|
|
* Bus read/write barrier methods.
|
|
*
|
|
* void bus_space_barrier (bus_space_tag_t tag,
|
|
* bus_space_handle_t bsh, bus_size_t offset,
|
|
* bus_size_t len, int flags);
|
|
*
|
|
*/
|
|
#define bus_space_barrier(t, h, o, l, f) \
|
|
((void)((void)(t), (void)(h), (void)(o), (void)(l), (void)(f)))
|
|
#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
|
|
#define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
|
|
|
|
#define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
|
|
|
|
/*
|
|
* Bus DMA methods.
|
|
*/
|
|
|
|
/*
|
|
* Flags used in various bus DMA methods.
|
|
*/
|
|
#define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */
|
|
#define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */
|
|
#define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */
|
|
/* Allow machine-dependent code to override BUS_DMA_COHERENT */
|
|
#ifndef BUS_DMA_COHERENT
|
|
#define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */
|
|
#endif
|
|
#define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */
|
|
#define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */
|
|
#define BUS_DMA_BUS2 0x020
|
|
#define BUS_DMA_BUS3 0x040
|
|
#define BUS_DMA_BUS4 0x080
|
|
#define BUS_DMA_READ 0x100 /* mapping is device -> memory only */
|
|
#define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */
|
|
#define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */
|
|
|
|
/* Forwards needed by prototypes below. */
|
|
struct proc;
|
|
struct mbuf;
|
|
struct uio;
|
|
|
|
/*
|
|
* Operations performed by bus_dmamap_sync().
|
|
*/
|
|
#define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */
|
|
#define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */
|
|
#define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */
|
|
#define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */
|
|
|
|
typedef struct powerpc_bus_dma_tag *bus_dma_tag_t;
|
|
typedef struct powerpc_bus_dmamap *bus_dmamap_t;
|
|
|
|
#define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0)
|
|
|
|
/*
|
|
* bus_dma_segment_t
|
|
*
|
|
* Describes a single contiguous DMA transaction. Values
|
|
* are suitable for programming into DMA registers.
|
|
*/
|
|
struct powerpc_bus_dma_segment {
|
|
bus_addr_t ds_addr; /* DMA address */
|
|
bus_size_t ds_len; /* length of transfer */
|
|
};
|
|
typedef struct powerpc_bus_dma_segment bus_dma_segment_t;
|
|
|
|
/*
|
|
* bus_dma_tag_t
|
|
*
|
|
* A machine-dependent opaque type describing the implementation of
|
|
* DMA for a given bus.
|
|
*/
|
|
|
|
struct powerpc_bus_dma_tag {
|
|
/*
|
|
* The `bounce threshold' is checked while we are loading
|
|
* the DMA map. If the physical address of the segment
|
|
* exceeds the threshold, an error will be returned. The
|
|
* caller can then take whatever action is necessary to
|
|
* bounce the transfer. If this value is 0, it will be
|
|
* ignored.
|
|
*/
|
|
bus_addr_t _bounce_thresh;
|
|
|
|
/*
|
|
* DMA mapping methods.
|
|
*/
|
|
int (*_dmamap_create) (bus_dma_tag_t, bus_size_t, int,
|
|
bus_size_t, bus_size_t, int, bus_dmamap_t *);
|
|
void (*_dmamap_destroy) (bus_dma_tag_t, bus_dmamap_t);
|
|
int (*_dmamap_load) (bus_dma_tag_t, bus_dmamap_t, void *,
|
|
bus_size_t, struct proc *, int);
|
|
int (*_dmamap_load_mbuf) (bus_dma_tag_t, bus_dmamap_t,
|
|
struct mbuf *, int);
|
|
int (*_dmamap_load_uio) (bus_dma_tag_t, bus_dmamap_t,
|
|
struct uio *, int);
|
|
int (*_dmamap_load_raw) (bus_dma_tag_t, bus_dmamap_t,
|
|
bus_dma_segment_t *, int, bus_size_t, int);
|
|
void (*_dmamap_unload) (bus_dma_tag_t, bus_dmamap_t);
|
|
void (*_dmamap_sync) (bus_dma_tag_t, bus_dmamap_t,
|
|
bus_addr_t, bus_size_t, int);
|
|
|
|
/*
|
|
* DMA memory utility functions.
|
|
*/
|
|
int (*_dmamem_alloc) (bus_dma_tag_t, bus_size_t, bus_size_t,
|
|
bus_size_t, bus_dma_segment_t *, int, int *, int);
|
|
void (*_dmamem_free) (bus_dma_tag_t,
|
|
bus_dma_segment_t *, int);
|
|
int (*_dmamem_map) (bus_dma_tag_t, bus_dma_segment_t *,
|
|
int, size_t, caddr_t *, int);
|
|
void (*_dmamem_unmap) (bus_dma_tag_t, caddr_t, size_t);
|
|
paddr_t (*_dmamem_mmap) (bus_dma_tag_t, bus_dma_segment_t *,
|
|
int, off_t, int, int);
|
|
|
|
#ifndef PHYS_TO_BUS_MEM
|
|
bus_addr_t (*_dma_phys_to_bus_mem)(bus_dma_tag_t, bus_addr_t);
|
|
#define PHYS_TO_BUS_MEM(t, addr) (*(t)->_dma_phys_to_bus_mem)((t), (addr))
|
|
#endif
|
|
#ifndef BUS_MEM_TO_PHYS
|
|
bus_addr_t (*_dma_bus_mem_to_phys)(bus_dma_tag_t, bus_addr_t);
|
|
#define BUS_MEM_TO_PHYS(t, addr) (*(t)->_dma_bus_mem_to_phys)((t), (addr))
|
|
#endif
|
|
};
|
|
|
|
#define bus_dmamap_create(t, s, n, m, b, f, p) \
|
|
(*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p))
|
|
#define bus_dmamap_destroy(t, p) \
|
|
(*(t)->_dmamap_destroy)((t), (p))
|
|
#define bus_dmamap_load(t, m, b, s, p, f) \
|
|
(*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f))
|
|
#define bus_dmamap_load_mbuf(t, m, b, f) \
|
|
(*(t)->_dmamap_load_mbuf)((t), (m), (b), (f))
|
|
#define bus_dmamap_load_uio(t, m, u, f) \
|
|
(*(t)->_dmamap_load_uio)((t), (m), (u), (f))
|
|
#define bus_dmamap_load_raw(t, m, sg, n, s, f) \
|
|
(*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f))
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#define bus_dmamap_unload(t, p) \
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(*(t)->_dmamap_unload)((t), (p))
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#define bus_dmamap_sync(t, p, o, l, ops) \
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(void)((t)->_dmamap_sync ? \
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(*(t)->_dmamap_sync)((t), (p), (o), (l), (ops)) : (void)0)
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|
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#define bus_dmamem_alloc(t, s, a, b, sg, n, r, f) \
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(*(t)->_dmamem_alloc)((t), (s), (a), (b), (sg), (n), (r), (f))
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#define bus_dmamem_free(t, sg, n) \
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(*(t)->_dmamem_free)((t), (sg), (n))
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#define bus_dmamem_map(t, sg, n, s, k, f) \
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(*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
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#define bus_dmamem_unmap(t, k, s) \
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(*(t)->_dmamem_unmap)((t), (k), (s))
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#define bus_dmamem_mmap(t, sg, n, o, p, f) \
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(*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f))
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|
|
|
/*
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|
* bus_dmamap_t
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|
*
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|
* Describes a DMA mapping.
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|
*/
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|
struct powerpc_bus_dmamap {
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|
/*
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|
* PRIVATE MEMBERS: not for use my machine-independent code.
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|
*/
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|
bus_size_t _dm_size; /* largest DMA transfer mappable */
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|
int _dm_segcnt; /* number of segs this map can map */
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|
bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */
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|
bus_size_t _dm_boundary; /* don't cross this */
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|
bus_addr_t _dm_bounce_thresh; /* bounce threshold; see tag */
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|
int _dm_flags; /* misc. flags */
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|
|
|
void *_dm_cookie; /* cookie for bus-specific functions */
|
|
|
|
/*
|
|
* PUBLIC MEMBERS: these are used by machine-independent code.
|
|
*/
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|
bus_size_t dm_maxsegsz; /* largest possible segment */
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|
bus_size_t dm_mapsize; /* size of the mapping */
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|
int dm_nsegs; /* # valid segments in mapping */
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|
bus_dma_segment_t dm_segs[1]; /* segments; variable length */
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|
};
|
|
|
|
#ifdef _POWERPC_BUS_DMA_PRIVATE
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|
int _bus_dmamap_create (bus_dma_tag_t, bus_size_t, int, bus_size_t,
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|
bus_size_t, int, bus_dmamap_t *);
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|
void _bus_dmamap_destroy (bus_dma_tag_t, bus_dmamap_t);
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|
int _bus_dmamap_load (bus_dma_tag_t, bus_dmamap_t, void *,
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|
bus_size_t, struct proc *, int);
|
|
int _bus_dmamap_load_mbuf (bus_dma_tag_t, bus_dmamap_t,
|
|
struct mbuf *, int);
|
|
int _bus_dmamap_load_uio (bus_dma_tag_t, bus_dmamap_t,
|
|
struct uio *, int);
|
|
int _bus_dmamap_load_raw (bus_dma_tag_t, bus_dmamap_t,
|
|
bus_dma_segment_t *, int, bus_size_t, int);
|
|
void _bus_dmamap_unload (bus_dma_tag_t, bus_dmamap_t);
|
|
void _bus_dmamap_sync (bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
|
|
bus_size_t, int);
|
|
|
|
int _bus_dmamem_alloc (bus_dma_tag_t tag, bus_size_t size,
|
|
bus_size_t alignment, bus_size_t boundary,
|
|
bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags);
|
|
void _bus_dmamem_free (bus_dma_tag_t tag, bus_dma_segment_t *segs,
|
|
int nsegs);
|
|
int _bus_dmamem_map (bus_dma_tag_t tag, bus_dma_segment_t *segs,
|
|
int nsegs, size_t size, caddr_t *kvap, int flags);
|
|
void _bus_dmamem_unmap (bus_dma_tag_t tag, caddr_t kva,
|
|
size_t size);
|
|
paddr_t _bus_dmamem_mmap (bus_dma_tag_t tag, bus_dma_segment_t *segs,
|
|
int nsegs, off_t off, int prot, int flags);
|
|
|
|
int _bus_dmamem_alloc_range (bus_dma_tag_t tag, bus_size_t size,
|
|
bus_size_t alignment, bus_size_t boundary,
|
|
bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags,
|
|
paddr_t low, paddr_t high);
|
|
bus_addr_t _bus_dma_phys_to_bus_mem_generic(bus_dma_tag_t, bus_addr_t);
|
|
bus_addr_t _bus_dma_bus_mem_to_phys_generic(bus_dma_tag_t, bus_addr_t);
|
|
#endif /* _POWERPC_BUS_DMA_PRIVATE */
|
|
#endif /* _POWERPC_BUS_H_ */
|