141 lines
5.7 KiB
C
141 lines
5.7 KiB
C
/* $NetBSD: intreg.h,v 1.6 1997/07/22 20:19:10 pk Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)intreg.h 8.1 (Berkeley) 6/11/93
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*/
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#include <sparc/sparc/vaddrs.h>
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/*
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* sun4c interrupt enable register.
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*
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* The register is a single byte. C code must use the ienab_bis and
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* ienab_bic functions found in locore.s.
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*
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* The register's physical address is defined here as the register
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* must be mapped early in the boot process (otherwise NMI handling
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* will fail).
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*/
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#define INT_ENABLE_REG_PHYSADR 0xf5000000 /* phys addr in IOspace */
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/*
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* Bits in interrupt enable register. Software interrupt requests must
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* be cleared in software. This is done in locore.s. The ALLIE bit must
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* be cleared to clear asynchronous memory error (level 15) interrupts.
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*/
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#define IE_L14 0x80 /* enable level 14 (counter 1) interrupts */
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#define IE_L10 0x20 /* enable level 10 (counter 0) interrupts */
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#define IE_L8 0x10 /* enable level 8 interrupts */
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#define IE_L6 0x08 /* request software level 6 interrupt */
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#define IE_L4 0x04 /* request software level 4 interrupt */
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#define IE_L1 0x02 /* request software level 1 interrupt */
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#define IE_ALLIE 0x01 /* enable interrupts */
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#ifndef _LOCORE
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void ienab_bis __P((int bis)); /* set given bits */
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void ienab_bic __P((int bic)); /* clear given bits */
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#endif
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#if defined(SUN4M)
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#ifdef notyet
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#define IENAB_SYS ((_MAXNBPG * _MAXNCPU) + 0xc)
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#define IENAB_P0 0x0008
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#define IENAB_P1 0x1008
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#define IENAB_P2 0x2008
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#define IENAB_P3 0x3008
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#endif /* notyet */
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#endif
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#if defined(SUN4M)
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/*
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* Interrupt Control Registers, located in IO space.
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* (mapped to `locore' for now..)
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* There are two sets of interrupt registers called `Processor Interrupts'
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* and `System Interrupts'. The `Processor' set corresponds to the 15
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* interrupt levels as seen by the CPU. The `System' set corresponds to
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* a set of devices supported by the implementing chip-set.
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*
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* Briefly, the ICR_PI_* are per-processor interrupts; the ICR_SI_* are
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* system-wide interrupts, and the ICR_ITR selects the processor to get
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* the system's interrupts.
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*/
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#define ICR_PI_PEND (PI_INTR_VA + 0x0)
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#define ICR_PI_CLR (PI_INTR_VA + 0x4)
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#define ICR_PI_SET (PI_INTR_VA + 0x8)
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#define ICR_SI_PEND (SI_INTR_VA)
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#define ICR_SI_MASK (SI_INTR_VA + 0x4)
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#define ICR_SI_CLR (SI_INTR_VA + 0x8)
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#define ICR_SI_SET (SI_INTR_VA + 0xc)
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#define ICR_ITR (SI_INTR_VA + 0x10)
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/*
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* Bits in interrupt registers. Software interrupt requests must
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* be cleared in software. This is done in locore.s.
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* There are separate registers for reading pending interrupts and
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* setting/clearing (software) interrupts.
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*/
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#define PINTR_SINTRLEV(n) (1 << (16 + (n)))
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#define PINTR_IC 0x8000 /* Level 15 clear */
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#define SINTR_MA 0x80000000 /* Mask All interrupts */
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#define SINTR_ME 0x40000000 /* Module Error (async) */
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#define SINTR_I 0x20000000 /* MSI (MBus-SBus) */
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#define SINTR_M 0x10000000 /* ECC Memory controller */
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#define SINTR_V 0x08000000 /* VME Async error */
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#define SINTR_RSVD2 0x07800000
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#define SINTR_F 0x00400000 /* Floppy */
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#define SINTR_MI 0x00200000 /* Module interrupt */
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#define SINTR_VI 0x00100000 /* Video (Supersparc only) */
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#define SINTR_T 0x00080000 /* Level 10 counter */
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#define SINTR_SC 0x00040000 /* SCSI */
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#define SINTR_A 0x00020000 /* Audio/ISDN */
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#define SINTR_E 0x00010000 /* Ethernet */
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#define SINTR_S 0x00008000 /* Serial port */
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#define SINTR_K 0x00004000 /* Keyboard/mouse */
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#define SINTR_SBUSMASK 0x00003f80 /* SBus */
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#define SINTR_SBUS(n) (1 << (7+(n)-1))
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#define SINTR_VMEMASK 0x0000007f /* VME */
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#define SINTR_VME(n) (1 << ((n)-1))
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#endif
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