fef3e76b31
similar design and code by Jason Thorpe and Jonathan Stone.
NOTE: the kernel-stack-switching code and cacheflush() calls in
locore.S still use #ifdef MIPS3 and need more work.
mips/include/cpu.h:
Add CPUISMIPS3 for run-time tests of what CPU architecture level
we're running on.
mips/include/locore.h:
Add declarations of locore cache-size variables for ref/def toolchain.
mips/include/mips1_pte.h:
mips1 TLB bit definitions.
mips/include/mips3_pte.h:
mips3 TLB bit definitions.
mips/include/pte.h:
define accesor macros for TLB bits (e.g., mips_pg_m_bit(),
that expand to CPU constants if only one CPU arch is configured,
or to inline functions if both MIPS1 and MIPS3 are configured.
mips/mips/locore_r2000.S:
Use MIPS1_PG_xxx constants inside mips1-specific code.
mips/mips/locore_r4000.S:
Use MIPS3_PG_xxx constants inside mips3-specific code.
mips/mips/locore.S:
Use MIPS1_PG_xxx constants inside mips3-specific code.
Use MIPS1_PG_xxx constants inside mips1-specific code.
(Needs more work!)
mips/mips/{pmap.c,vm_machdep.c,trap.c}, pmax/pmax/machdep.c:
Use MIPS3_PG_xxx constants inside mips3-specific functions,
and MIPS1_PG_XXX inside mips1-specific code.
Otherwise, use mips_pg_XXX_bit() macros where they apply,
and use "if (CPUISMIPS3) { ... } else {... }" where they don't.
mips/mips/mips_machdep.c:
Import Michael Hitch's fixes from the pmax locore-init code
into mips_vector_init().
pmax/pmax/machdep.c:
Use generic mips_vector_init() locore vector-init function.
128 lines
4.7 KiB
C
128 lines
4.7 KiB
C
/* $NetBSD: mips3_pte.h,v 1.7 1997/06/16 23:41:44 jonathan Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department and Ralph Campbell.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: Utah Hdr: pte.h 1.11 89/09/03
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*
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* from: @(#)pte.h 8.1 (Berkeley) 6/10/93
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*/
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/*
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* R4000 hardware page table entry
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*/
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#ifndef _LOCORE
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struct mips3_pte {
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#if BYTE_ORDER == BIG_ENDIAN
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unsigned int pg_prot:2, /* SW: access control */
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pg_pfnum:24, /* HW: core page frame number or 0 */
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pg_attr:3, /* HW: cache attribute */
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pg_m:1, /* HW: modified (dirty) bit */
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pg_v:1, /* HW: valid bit */
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pg_g:1; /* HW: ignore pid bit */
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#endif
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#if BYTE_ORDER == LITTLE_ENDIAN
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unsigned int pg_g:1, /* HW: ignore pid bit */
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pg_v:1, /* HW: valid bit */
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pg_m:1, /* HW: modified (dirty) bit */
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pg_attr:3, /* HW: cache attribute */
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pg_pfnum:24, /* HW: core page frame number or 0 */
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pg_prot:2; /* SW: access control */
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#endif
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};
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/*
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* Structure defining an tlb entry data set.
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*/
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struct tlb {
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int tlb_mask;
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int tlb_hi;
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int tlb_lo0;
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int tlb_lo1;
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};
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#endif /* _LOCORE */
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#define MIPS3_PG_WIRED 0x80000000 /* SW */
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#define MIPS3_PG_RO 0x40000000 /* SW */
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#define MIPS3_PG_SVPN 0xfffff000 /* Software page no mask */
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#define MIPS3_PG_HVPN 0xffffe000 /* Hardware page no mask */
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#define MIPS3_PG_ODDPG 0x00001000 /* Odd even pte entry */
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#define MIPS3_PG_ASID 0x000000ff /* Address space ID */
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#define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
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#define MIPS3_PG_V 0x00000002 /* Valid */
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#define MIPS3_PG_NV 0x00000000
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#define MIPS3_PG_M 0x00000004 /* Dirty; i.e. writable */
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#define MIPS3_PG_ATTR 0x0000003f
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#define MIPS3_PG_UNCACHED 0x00000010
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#define MIPS3_PG_CACHED 0x00000018 /* Cacheable noncoherent */
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#define MIPS3_PG_CACHEMODE 0x00000038
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/* Write protected */
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#define MIPS3_PG_ROPAGE (MIPS3_PG_V | MIPS3_PG_RO | MIPS3_PG_CACHED)
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/* Not wr-prot not clean */
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#define MIPS3_PG_RWPAGE (MIPS3_PG_V | MIPS3_PG_M | MIPS3_PG_CACHED)
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/* Not wr-prot but clean */
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#define MIPS3_PG_CWPAGE (MIPS3_PG_V | MIPS3_PG_CACHED)
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#define MIPS3_PG_IOPAGE \
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(MIPS3_PG_G | MIPS3_PG_V | MIPS3_PG_M | MIPS3_PG_UNCACHED)
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#define MIPS3_PG_FRAME 0x3fffffc0
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#define MIPS3_PG_SHIFT 6
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/* pte accessor macros */
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#define mips3_vad_to_pfn(x) (((unsigned)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
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#define mips3_pfn_to_vad(x) (((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
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#define mips3_vad_to_vpn(x) ((unsigned)(x) & MIPS3_PG_SVPN)
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#define mips3_vpn_to_vad(x) ((x) & MIPS3_PG_SVPN)
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#define MIPS3_PTE_TO_PADDR(pte) (mips3_pfn_to_vad(pte))
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#define MIPS3_PAGE_IS_RDONLY(pte,va) \
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(pmap_is_page_ro(pmap_kernel(), mips_trunc_page(va), (pte)))
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#define MIPS3_PG_SIZE_4K 0x00000000
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#define MIPS3_PG_SIZE_16K 0x00006000
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#define MIPS3_PG_SIZE_64K 0x0001e000
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#define MIPS3_PG_SIZE_256K 0x0007e000
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#define MIPS3_PG_SIZE_1M 0x001fe000
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#define MIPS3_PG_SIZE_4M 0x007fe000
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#define MIPS3_PG_SIZE_16M 0x01ffe000
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