15d4cf6bf9
amiga goes: config.new *and* /sys/scsi. clock code coerced into a single .c file adding an accurate usec delay(). disklabel.c updated to DTRT, code to write RDB's to be added soon. sbic (old scsi) converted over to new scsi and config this covers about 90% of users. Other drivers soon.
424 lines
16 KiB
C
424 lines
16 KiB
C
/*
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Van Jacobson of Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)scsireg.h 7.3 (Berkeley) 2/5/91
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* $Id: sbicreg.h,v 1.1 1994/05/08 05:53:38 chopps Exp $
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*/
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/*
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* AMD AM33C93A SCSI interface hardware description.
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*
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* Using parts of the Mach scsi driver for the 33C93
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*/
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#define SBIC_myid 0
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#define SBIC_cdbsize 0
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#define SBIC_control 1
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#define SBIC_timeo 2
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#define SBIC_cdb1 3
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#define SBIC_tsecs 3
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#define SBIC_cdb2 4
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#define SBIC_theads 4
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#define SBIC_cdb3 5
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#define SBIC_tcyl_hi 5
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#define SBIC_cdb4 6
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#define SBIC_tcyl_lo 6
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#define SBIC_cdb5 7
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#define SBIC_addr_hi 7
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#define SBIC_cdb6 8
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#define SBIC_addr_2 8
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#define SBIC_cdb7 9
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#define SBIC_addr_3 9
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#define SBIC_cdb8 10
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#define SBIC_addr_lo 10
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#define SBIC_cdb9 11
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#define SBIC_secno 11
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#define SBIC_cdb10 12
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#define SBIC_headno 12
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#define SBIC_cdb11 13
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#define SBIC_cylno_hi 13
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#define SBIC_cdb12 14
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#define SBIC_cylno_lo 14
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#define SBIC_tlun 15
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#define SBIC_cmd_phase 16
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#define SBIC_syn 17
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#define SBIC_count_hi 18
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#define SBIC_count_med 19
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#define SBIC_count_lo 20
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#define SBIC_selid 21
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#define SBIC_rselid 22
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#define SBIC_csr 23
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#define SBIC_cmd 24
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#define SBIC_data 25
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/* sbic_asr is addressed directly */
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/*
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* Register defines
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*/
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/*
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* Auxiliary Status Register
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*/
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#define SBIC_ASR_INT 0x80 /* Interrupt pending */
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#define SBIC_ASR_LCI 0x40 /* Last command ignored */
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#define SBIC_ASR_BSY 0x20 /* Busy, only cmd/data/asr readable */
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#define SBIC_ASR_CIP 0x10 /* Busy, cmd unavail also */
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#define SBIC_ASR_xxx 0x0c
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#define SBIC_ASR_PE 0x02 /* Parity error (even) */
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#define SBIC_ASR_DBR 0x01 /* Data Buffer Ready */
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/*
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* My ID register, and/or CDB Size
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*/
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#define SBIC_ID_FS_8_10 0x00 /* Input clock is 8-10 Mhz */
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/* 11 Mhz is invalid */
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#define SBIC_ID_FS_12_15 0x40 /* Input clock is 12-15 Mhz */
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#define SBIC_ID_FS_16_20 0x80 /* Input clock is 16-20 Mhz */
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#define SBIC_ID_EHP 0x10 /* Enable host parity */
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#define SBIC_ID_EAF 0x08 /* Enable Advanced Features */
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#define SBIC_ID_MASK 0x07
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#define SBIC_ID_CBDSIZE_MASK 0x0f /* if unk SCSI cmd group */
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/*
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* Control register
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*/
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#define SBIC_CTL_DMA 0x80 /* Single byte dma */
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#define SBIC_CTL_DBA_DMA 0x40 /* direct buffer acces (bus master)*/
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#define SBIC_CTL_BURST_DMA 0x20 /* continuous mode (8237) */
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#define SBIC_CTL_NO_DMA 0x00 /* Programmed I/O */
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#define SBIC_CTL_HHP 0x10 /* Halt on host parity error */
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#define SBIC_CTL_EDI 0x08 /* Ending disconnect interrupt */
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#define SBIC_CTL_IDI 0x04 /* Intermediate disconnect interrupt*/
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#define SBIC_CTL_HA 0x02 /* Halt on ATN */
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#define SBIC_CTL_HSP 0x01 /* Halt on SCSI parity error */
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/*
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* Timeout period register
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* [val in msecs, input clk in 0.1 Mhz]
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*/
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#define SBIC_TIMEOUT(val,clk) ((((val) * (clk)) / 800) + 1)
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/*
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* CDBn registers, note that
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* cdb11 is used for status byte in target mode (send-status-and-cc)
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* cdb12 sez if linked command complete, and w/flag if so
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*/
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/*
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* Target LUN register
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* [holds target status when select-and-xfer]
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*/
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#define SBIC_TLUN_VALID 0x80 /* did we receive an Identify msg */
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#define SBIC_TLUN_DOK 0x40 /* Disconnect OK */
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#define SBIC_TLUN_xxx 0x38
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#define SBIC_TLUN_MASK 0x07
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/*
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* Command Phase register
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*/
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#define SBIC_CPH_MASK 0x7f /* values/restarts are cmd specific */
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#define SBIC_CPH(p) ((p) & SBIC_CPH_MASK)
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/*
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* FIFO register
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*/
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#define SBIC_FIFO_DEEP 12
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/*
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* maximum possible size in TC registers. Since this is 24 bit, it's easy
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*/
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#define SBIC_TC_MAX ((1 << 24) - 1)
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/*
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* Synchronous xfer register
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*/
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#define SBIC_SYN_OFF_MASK 0x0f
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#define SBIC_SYN_MAX_OFFSET SBIC_FIFO_DEEP
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#define SBIC_SYN_PER_MASK 0x70
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#define SBIC_SYN_MIN_PERIOD 2 /* upto 8, encoded as 0 */
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#define SBIC_SYN(o,p) \
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(((o) & SBIC_SYN_OFF_MASK) | (((p) << 4) & SBIC_SYN_PER_MASK))
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/*
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* Transfer count register
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* optimal access macros depend on addressing
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*/
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/*
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* Destination ID (selid) register
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*/
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#define SBIC_SID_SCC 0x80 /* Select command chaining (tgt) */
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#define SBIC_SID_DPD 0x40 /* Data phase direction (inittor) */
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#define SBIC_SID_FROM_SCSI 0x40
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#define SBIC_SID_TO_SCSI 0x00
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#define SBIC_SID_xxx 0x38
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#define SBIC_SID_IDMASK 0x07
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/*
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* Source ID (rselid) register
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*/
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#define SBIC_RID_ER 0x80 /* Enable reselection */
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#define SBIC_RID_ES 0x40 /* Enable selection */
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#define SBIC_RID_DSP 0x20 /* Disable select parity */
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#define SBIC_RID_SIV 0x08 /* Source ID valid */
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#define SBIC_RID_MASK 0x07
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/*
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* Status register
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*/
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#define SBIC_CSR_CAUSE 0xf0
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#define SBIC_CSR_RESET 0x00 /* chip was reset */
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#define SBIC_CSR_CMD_DONE 0x10 /* cmd completed */
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#define SBIC_CSR_CMD_STOPPED 0x20 /* interrupted or abrted*/
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#define SBIC_CSR_CMD_ERR 0x40 /* end with error */
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#define SBIC_CSR_BUS_SERVICE 0x80 /* REQ pending on the bus */
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#define SBIC_CSR_QUALIFIER 0x0f
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/* Reset State Interrupts */
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#define SBIC_CSR_RESET 0x00 /* reset w/advanced features*/
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#define SBIC_CSR_RESET_AM 0x01 /* reset w/advanced features*/
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/* Successful Completion Interrupts */
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#define SBIC_CSR_TARGET 0x10 /* reselect complete */
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#define SBIC_CSR_INITIATOR 0x11 /* select complete */
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#define SBIC_CSR_WO_ATN 0x13 /* tgt mode completion */
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#define SBIC_CSR_W_ATN 0x14 /* ditto */
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#define SBIC_CSR_XLATED 0x15 /* translate address cmd */
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#define SBIC_CSR_S_XFERRED 0x16 /* initiator mode completion*/
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#define SBIC_CSR_XFERRED 0x18 /* phase in low bits */
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/* Paused or Aborted Interrupts */
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#define SBIC_CSR_MSGIN_W_ACK 0x20 /* (I) msgin, ACK asserted*/
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#define SBIC_CSR_SDP 0x21 /* (I) SDP msg received */
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#define SBIC_CSR_SEL_ABRT 0x22 /* sel/resel aborted */
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#define SBIC_CSR_XFR_PAUSED 0x23 /* (T) no ATN */
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#define SBIC_CSR_XFR_PAUSED_ATN 0x24 /* (T) ATN is asserted */
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#define SBIC_CSR_RSLT_AM 0x27 /* (I) lost selection (AM) */
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#define SBIC_CSR_MIS 0x28 /* (I) xfer aborted, ph mis */
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/* Terminated Interrupts */
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#define SBIC_CSR_CMD_INVALID 0x40
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#define SBIC_CSR_DISC 0x41 /* (I) tgt disconnected */
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#define SBIC_CSR_SEL_TIMEO 0x42
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#define SBIC_CSR_PE 0x43 /* parity error */
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#define SBIC_CSR_PE_ATN 0x44 /* ditto, ATN is asserted */
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#define SBIC_CSR_XLATE_TOOBIG 0x45
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#define SBIC_CSR_RSLT_NOAM 0x46 /* (I) lost sel, no AM mode */
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#define SBIC_CSR_BAD_STATUS 0x47 /* status byte was nok */
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#define SBIC_CSR_MIS_1 0x48 /* ph mis, see low bits */
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/* Service Required Interrupts */
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#define SBIC_CSR_RSLT_NI 0x80 /* reselected, no ify msg */
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#define SBIC_CSR_RSLT_IFY 0x81 /* ditto, AM mode, got ify */
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#define SBIC_CSR_SLT 0x82 /* selected, no ATN */
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#define SBIC_CSR_SLT_ATN 0x83 /* selected with ATN */
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#define SBIC_CSR_ATN 0x84 /* (T) ATN asserted */
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#define SBIC_CSR_DISC_1 0x85 /* (I) bus is free */
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#define SBIC_CSR_UNK_GROUP 0x87 /* strange CDB1 */
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#define SBIC_CSR_MIS_2 0x88 /* (I) ph mis, see low bits */
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#define SBIC_PHASE(csr) SCSI_PHASE(csr)
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/*
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* Command register (command codes)
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*/
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#define SBIC_CMD_SBT 0x80 /* Single byte xfer qualifier */
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#define SBIC_CMD_MASK 0x7f
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/* Miscellaneous */
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#define SBIC_CMD_RESET 0x00 /* (DTI) lev I */
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#define SBIC_CMD_ABORT 0x01 /* (DTI) lev I */
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#define SBIC_CMD_DISC 0x04 /* ( TI) lev I */
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#define SBIC_CMD_SSCC 0x0d /* ( TI) lev I */
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#define SBIC_CMD_SET_IDI 0x0f /* (DTI) lev I */
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#define SBIC_CMD_XLATE 0x18 /* (DT ) lev II */
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/* Initiator state */
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#define SBIC_CMD_SET_ATN 0x02 /* ( I) lev I */
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#define SBIC_CMD_CLR_ACK 0x03 /* ( I) lev I */
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#define SBIC_CMD_XFER_PAD 0x19 /* ( I) lev II */
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#define SBIC_CMD_XFER_INFO 0x20 /* ( I) lev II */
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/* Target state */
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#define SBIC_CMD_SND_DISC 0x0e /* ( T ) lev II */
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#define SBIC_CMD_RCV_CMD 0x10 /* ( T ) lev II */
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#define SBIC_CMD_RCV_DATA 0x11 /* ( T ) lev II */
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#define SBIC_CMD_RCV_MSG_OUT 0x12 /* ( T ) lev II */
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#define SBIC_CMD_RCV 0x13 /* ( T ) lev II */
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#define SBIC_CMD_SND_STATUS 0x14 /* ( T ) lev II */
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#define SBIC_CMD_SND_DATA 0x15 /* ( T ) lev II */
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#define SBIC_CMD_SND_MSG_IN 0x16 /* ( T ) lev II */
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#define SBIC_CMD_SND 0x17 /* ( T ) lev II */
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/* Disconnected state */
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#define SBIC_CMD_RESELECT 0x05 /* (D ) lev II */
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#define SBIC_CMD_SEL_ATN 0x06 /* (D ) lev II */
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#define SBIC_CMD_SEL 0x07 /* (D ) lev II */
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#define SBIC_CMD_SEL_ATN_XFER 0x08 /* (D I) lev II */
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#define SBIC_CMD_SEL_XFER 0x09 /* (D I) lev II */
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#define SBIC_CMD_RESELECT_RECV 0x0a /* (DT ) lev II */
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#define SBIC_CMD_RESELECT_SEND 0x0b /* (DT ) lev II */
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#define SBIC_CMD_WAIT_SEL_RECV 0x0c /* (DT ) lev II */
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/* approximate, but we won't do SBT on selects */
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#define sbic_isa_select(cmd) (((cmd) > 0x5) && ((cmd) < 0xa))
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#define PAD(n) char n;
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#define SBIC_MACHINE_DMA_MODE SBIC_CTL_DMA
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typedef struct {
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volatile unsigned char sbic_asr; /* r : Aux Status Register */
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#define sbic_address sbic_asr /* w : desired register no */
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PAD(pad1);
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volatile unsigned char sbic_value; /* rw: register value */
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} sbic_padded_ind_regmap_t;
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typedef volatile sbic_padded_ind_regmap_t *sbic_regmap_p;
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#define sbic_read_reg(regs,regno,val) do { \
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(regs)->sbic_address = (regno); \
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(val) = (regs)->sbic_value; \
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} while (0)
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#define sbic_write_reg(regs,regno,val) do { \
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(regs)->sbic_address = (regno); \
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(regs)->sbic_value = (val); \
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} while (0)
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#define SET_SBIC_myid(regs,val) sbic_write_reg(regs,SBIC_myid,val)
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#define GET_SBIC_myid(regs,val) sbic_read_reg(regs,SBIC_myid,val)
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#define SET_SBIC_cdbsize(regs,val) sbic_write_reg(regs,SBIC_cdbsize,val)
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#define GET_SBIC_cdbsize(regs,val) sbic_read_reg(regs,SBIC_cdbsize,val)
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#define SET_SBIC_control(regs,val) sbic_write_reg(regs,SBIC_control,val)
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#define GET_SBIC_control(regs,val) sbic_read_reg(regs,SBIC_control,val)
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#define SET_SBIC_timeo(regs,val) sbic_write_reg(regs,SBIC_timeo,val)
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#define GET_SBIC_timeo(regs,val) sbic_read_reg(regs,SBIC_timeo,val)
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#define SET_SBIC_cdb1(regs,val) sbic_write_reg(regs,SBIC_cdb1,val)
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#define GET_SBIC_cdb1(regs,val) sbic_read_reg(regs,SBIC_cdb1,val)
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#define SET_SBIC_cdb2(regs,val) sbic_write_reg(regs,SBIC_cdb2,val)
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#define GET_SBIC_cdb2(regs,val) sbic_read_reg(regs,SBIC_cdb2,val)
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#define SET_SBIC_cdb3(regs,val) sbic_write_reg(regs,SBIC_cdb3,val)
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#define GET_SBIC_cdb3(regs,val) sbic_read_reg(regs,SBIC_cdb3,val)
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#define SET_SBIC_cdb4(regs,val) sbic_write_reg(regs,SBIC_cdb4,val)
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#define GET_SBIC_cdb4(regs,val) sbic_read_reg(regs,SBIC_cdb4,val)
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#define SET_SBIC_cdb5(regs,val) sbic_write_reg(regs,SBIC_cdb5,val)
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#define GET_SBIC_cdb5(regs,val) sbic_read_reg(regs,SBIC_cdb5,val)
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#define SET_SBIC_cdb6(regs,val) sbic_write_reg(regs,SBIC_cdb6,val)
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#define GET_SBIC_cdb6(regs,val) sbic_read_reg(regs,SBIC_cdb6,val)
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#define SET_SBIC_cdb7(regs,val) sbic_write_reg(regs,SBIC_cdb7,val)
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#define GET_SBIC_cdb7(regs,val) sbic_read_reg(regs,SBIC_cdb7,val)
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#define SET_SBIC_cdb8(regs,val) sbic_write_reg(regs,SBIC_cdb8,val)
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#define GET_SBIC_cdb8(regs,val) sbic_read_reg(regs,SBIC_cdb8,val)
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#define SET_SBIC_cdb9(regs,val) sbic_write_reg(regs,SBIC_cdb9,val)
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#define GET_SBIC_cdb9(regs,val) sbic_read_reg(regs,SBIC_cdb9,val)
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#define SET_SBIC_cdb10(regs,val) sbic_write_reg(regs,SBIC_cdb10,val)
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#define GET_SBIC_cdb10(regs,val) sbic_read_reg(regs,SBIC_cdb10,val)
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#define SET_SBIC_cdb11(regs,val) sbic_write_reg(regs,SBIC_cdb11,val)
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#define GET_SBIC_cdb11(regs,val) sbic_read_reg(regs,SBIC_cdb11,val)
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#define SET_SBIC_cdb12(regs,val) sbic_write_reg(regs,SBIC_cdb12,val)
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#define GET_SBIC_cdb12(regs,val) sbic_read_reg(regs,SBIC_cdb12,val)
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#define SET_SBIC_tlun(regs,val) sbic_write_reg(regs,SBIC_tlun,val)
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#define GET_SBIC_tlun(regs,val) sbic_read_reg(regs,SBIC_tlun,val)
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#define SET_SBIC_cmd_phase(regs,val) sbic_write_reg(regs,SBIC_cmd_phase,val)
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#define GET_SBIC_cmd_phase(regs,val) sbic_read_reg(regs,SBIC_cmd_phase,val)
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#define SET_SBIC_syn(regs,val) sbic_write_reg(regs,SBIC_syn,val)
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#define GET_SBIC_syn(regs,val) sbic_read_reg(regs,SBIC_syn,val)
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#define SET_SBIC_count_hi(regs,val) sbic_write_reg(regs,SBIC_count_hi,val)
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#define GET_SBIC_count_hi(regs,val) sbic_read_reg(regs,SBIC_count_hi,val)
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#define SET_SBIC_count_med(regs,val) sbic_write_reg(regs,SBIC_count_med,val)
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#define GET_SBIC_count_med(regs,val) sbic_read_reg(regs,SBIC_count_med,val)
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#define SET_SBIC_count_lo(regs,val) sbic_write_reg(regs,SBIC_count_lo,val)
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#define GET_SBIC_count_lo(regs,val) sbic_read_reg(regs,SBIC_count_lo,val)
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#define SET_SBIC_selid(regs,val) sbic_write_reg(regs,SBIC_selid,val)
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#define GET_SBIC_selid(regs,val) sbic_read_reg(regs,SBIC_selid,val)
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#define SET_SBIC_rselid(regs,val) sbic_write_reg(regs,SBIC_rselid,val)
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#define GET_SBIC_rselid(regs,val) sbic_read_reg(regs,SBIC_rselid,val)
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#define SET_SBIC_csr(regs,val) sbic_write_reg(regs,SBIC_csr,val)
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#define GET_SBIC_csr(regs,val) sbic_read_reg(regs,SBIC_csr,val)
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#define SET_SBIC_cmd(regs,val) sbic_write_reg(regs,SBIC_cmd,val)
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#define GET_SBIC_cmd(regs,val) sbic_read_reg(regs,SBIC_cmd,val)
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#define SET_SBIC_data(regs,val) sbic_write_reg(regs,SBIC_data,val)
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#define GET_SBIC_data(regs,val) sbic_read_reg(regs,SBIC_data,val)
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#define SBIC_TC_PUT(regs,val) do { \
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sbic_write_reg(regs,SBIC_count_hi,((val)>>16)); \
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(regs)->sbic_value = (val)>>8; \
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(regs)->sbic_value = (val); \
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} while (0)
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#define SBIC_TC_GET(regs,val) do { \
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sbic_read_reg(regs,SBIC_count_hi,(val)); \
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(val) = ((val)<<8) | (regs)->sbic_value; \
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(val) = ((val)<<8) | (regs)->sbic_value; \
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} while (0)
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#define SBIC_LOAD_COMMAND(regs,cmd,cmdsize) do { \
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int n=(cmdsize)-1; \
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char *ptr = (char*)(cmd); \
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sbic_write_reg(regs,SBIC_cdb1,*ptr++); \
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while (n-- > 0) (regs)->sbic_value = *ptr++; \
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} while (0)
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#define GET_SBIC_asr(regs,val) (val) = (regs)->sbic_asr
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#define WAIT_CIP(regs) do { \
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while ((regs)->sbic_asr & SBIC_ASR_CIP) \
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; \
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} while (0)
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/* transmit a byte in programmed I/O mode */
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#define SEND_BYTE(regs, ch) do { \
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WAIT_CIP(regs); \
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SET_SBIC_cmd(regs, SBIC_CMD_SBT | SBIC_CMD_XFER_INFO); \
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SBIC_WAIT(regs, SBIC_ASR_DBR, 0); \
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SET_SBIC_data(regs, ch); \
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} while (0)
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/* receive a byte in programmed I/O mode */
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#define RECV_BYTE(regs, ch) do { \
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WAIT_CIP(regs); \
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SET_SBIC_cmd(regs, SBIC_CMD_SBT | SBIC_CMD_XFER_INFO); \
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SBIC_WAIT(regs, SBIC_ASR_DBR, 0); \
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GET_SBIC_data(regs, ch); \
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} while (0)
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