1101 lines
40 KiB
C
1101 lines
40 KiB
C
/* $NetBSD: rtwreg.h,v 1.19 2006/03/10 23:37:35 dyoung Exp $ */
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/*-
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* Copyright (c) 2004, 2005 David Young. All rights reserved.
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*
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* Programmed for NetBSD by David Young.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of David Young may not be used to endorse or promote
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* products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David
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* Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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#include <lib/libkern/libkern.h>
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/* RTL8180L Host Control and Status Registers */
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#define RTW_IDR0 0x00 /* ID Register: MAC addr, 6 bytes.
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* Auto-loaded from EEPROM. Read by byte,
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* by word, or by double word, but write
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* only by double word.
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*/
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#define RTW_IDR1 0x04
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#define RTW_MAR0 0x08 /* Multicast filter, 64b. */
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#define RTW_MAR1 0x0c
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#define RTW_TSFTRL 0x18 /* Timing Synchronization Function Timer
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* Register, low word, 32b, read-only.
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*/
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#define RTW_TSFTRH 0x1c /* High word, 32b, read-only. */
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#define RTW_TLPDA 0x20 /* Transmit Low Priority Descriptors Start
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* Address, 32b, 256-byte alignment.
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*/
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#define RTW_TNPDA 0x24 /* Transmit Normal Priority Descriptors Start
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* Address, 32b, 256-byte alignment.
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*/
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#define RTW_THPDA 0x28 /* Transmit High Priority Descriptors Start
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* Address, 32b, 256-byte alignment.
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*/
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#define RTW_BRSR 0x2c /* Basic Rate Set Register, 16b */
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#define RTW_BRSR_BPLCP __BIT(8)/* 1: use short PLCP header for CTS/ACK packet,
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* 0: use long PLCP header
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*/
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#define RTW_BRSR_MBR8180_MASK __BITS(1,0) /* Maximum Basic Service Rate */
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#define RTW_BRSR_MBR8180_1MBPS SHIFTIN(0, RTW_BRSR_MBR8180_MASK)
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#define RTW_BRSR_MBR8180_2MBPS SHIFTIN(1, RTW_BRSR_MBR8180_MASK)
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#define RTW_BRSR_MBR8180_5MBPS SHIFTIN(2, RTW_BRSR_MBR8180_MASK)
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#define RTW_BRSR_MBR8180_11MBPS SHIFTIN(3, RTW_BRSR_MBR8180_MASK)
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/* 8181 and 8180 docs conflict! */
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#define RTW_BRSR_MBR8181_1MBPS __BIT(0)
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#define RTW_BRSR_MBR8181_2MBPS __BIT(1)
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#define RTW_BRSR_MBR8181_5MBPS __BIT(2)
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#define RTW_BRSR_MBR8181_11MBPS __BIT(3)
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#define RTW_BSSID 0x2e
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/* BSSID, 6 bytes */
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#define RTW_BSSID16 0x2e /* first two bytes */
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#define RTW_BSSID32 (0x2e + 4) /* remaining four bytes */
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#define RTW_BSSID0 RTW_BSSID16 /* BSSID[0], 8b */
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#define RTW_BSSID1 (RTW_BSSID0 + 1) /* BSSID[1], 8b */
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#define RTW_BSSID2 (RTW_BSSID1 + 1) /* BSSID[2], 8b */
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#define RTW_BSSID3 (RTW_BSSID2 + 1) /* BSSID[3], 8b */
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#define RTW_BSSID4 (RTW_BSSID3 + 1) /* BSSID[4], 8b */
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#define RTW_BSSID5 (RTW_BSSID4 + 1) /* BSSID[5], 8b */
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#define RTW_CR 0x37 /* Command Register, 8b */
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#define RTW_CR_RST __BIT(4)/* Reset: host sets to 1 to disable
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* transmitter & receiver, reinitialize FIFO.
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* RTL8180L sets to 0 to signal completion.
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*/
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#define RTW_CR_RE __BIT(3)/* Receiver Enable: host enables receiver
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* by writing 1. RTL8180L indicates receiver
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* is active with 1. After power-up, host
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* must wait for reset before writing.
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*/
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#define RTW_CR_TE __BIT(2)/* Transmitter Enable: host enables transmitter
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* by writing 1. RTL8180L indicates transmitter
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* is active with 1. After power-up, host
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* must wait for reset before writing.
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*/
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#define RTW_CR_MULRW __BIT(0)/* PCI Multiple Read/Write enable: 1 enables,
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* 0 disables. XXX RTL8180, only?
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*/
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#define RTW_IMR 0x3c /* Interrupt Mask Register, 16b */
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#define RTW_ISR 0x3e /* Interrupt status register, 16b */
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#define RTW_INTR_TXFOVW __BIT(15) /* Tx FIFO underflow */
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#define RTW_INTR_TIMEOUT __BIT(14) /* Time Out: 1 indicates
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* RTW_TSFTR[0:31] = RTW_TINT
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*/
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/* Beacon Time Out: time for host to prepare beacon:
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* RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) =
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* (RTW_BCNITV_BCNITV * TU - RTW_BINTRITV)
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*/
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#define RTW_INTR_BCNINT __BIT(13)
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/* ATIM Time Out: ATIM interval will pass,
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* RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) =
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* (RTW_ATIMWND_ATIMWND * TU - RTW_ATIMTRITV)
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*/
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#define RTW_INTR_ATIMINT __BIT(12)
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/* Tx Beacon Descriptor Error: beacon transmission aborted because frame Rx'd */
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#define RTW_INTR_TBDER __BIT(11)
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#define RTW_INTR_TBDOK __BIT(10) /* Tx Beacon Descriptor OK */
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#define RTW_INTR_THPDER __BIT(9)/* Tx High Priority Descriptor Error:
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* reached short/long retry limit
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*/
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#define RTW_INTR_THPDOK __BIT(8)/* Tx High Priority Descriptor OK */
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#define RTW_INTR_TNPDER __BIT(7)/* Tx Normal Priority Descriptor Error:
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* reached short/long retry limit
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*/
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#define RTW_INTR_TNPDOK __BIT(6)/* Tx Normal Priority Descriptor OK */
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#define RTW_INTR_RXFOVW __BIT(5)/* Rx FIFO Overflow: either RDU (see below)
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* or PCI bus too slow/busy
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*/
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#define RTW_INTR_RDU __BIT(4)/* Rx Descriptor Unavailable */
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#define RTW_INTR_TLPDER __BIT(3)/* Tx Normal Priority Descriptor Error
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* reached short/long retry limit
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*/
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#define RTW_INTR_TLPDOK __BIT(2)/* Tx Normal Priority Descriptor OK */
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#define RTW_INTR_RER __BIT(1)/* Rx Error: CRC32 or ICV error */
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#define RTW_INTR_ROK __BIT(0)/* Rx OK */
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/* Convenient interrupt conjunctions. */
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#define RTW_INTR_RX (RTW_INTR_RER|RTW_INTR_ROK)
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#define RTW_INTR_TX (RTW_INTR_TLPDER|RTW_INTR_TLPDOK|RTW_INTR_THPDER|\
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RTW_INTR_THPDOK|RTW_INTR_TNPDER|RTW_INTR_TNPDOK|\
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RTW_INTR_TBDER|RTW_INTR_TBDOK)
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#define RTW_INTR_BEACON (RTW_INTR_BCNINT|RTW_INTR_TBDER|RTW_INTR_TBDOK)
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#define RTW_INTR_IOERROR (RTW_INTR_TXFOVW|RTW_INTR_RXFOVW|RTW_INTR_RDU)
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#define RTW_TCR 0x40 /* Transmit Configuration Register, 32b */
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#define RTW_TCR_CWMIN __BIT(31)/* 1: CWmin = 8, 0: CWmin = 32. */
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#define RTW_TCR_SWSEQ __BIT(30)/* 1: host assigns 802.11 sequence number,
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* 0: hardware assigns sequence number
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*/
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/* Hardware version ID, read-only */
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#define RTW_TCR_HWVERID_MASK __BITS(29, 25)
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#define RTW_TCR_HWVERID_D SHIFTIN(26, RTW_TCR_HWVERID_MASK)
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#define RTW_TCR_HWVERID_F SHIFTIN(27, RTW_TCR_HWVERID_MASK)
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#define RTW_TCR_HWVERID_RTL8180 RTW_TCR_HWVERID_F
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/* Set ACK/CTS Timeout (EIFS).
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* 1: ACK rate = max(RTW_BRSR_MBR, Rx rate) (XXX not min? typo in datasheet?)
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* 0: ACK rate = 1Mbps
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*/
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#define RTW_TCR_SAT __BIT(24)
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/* Max DMA Burst Size per Tx DMA Burst */
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#define RTW_TCR_MXDMA_MASK __BITS(23,21)
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#define RTW_TCR_MXDMA_16 SHIFTIN(0, RTW_TCR_MXDMA_MASK)
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#define RTW_TCR_MXDMA_32 SHIFTIN(1, RTW_TCR_MXDMA_MASK)
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#define RTW_TCR_MXDMA_64 SHIFTIN(2, RTW_TCR_MXDMA_MASK)
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#define RTW_TCR_MXDMA_128 SHIFTIN(3, RTW_TCR_MXDMA_MASK)
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#define RTW_TCR_MXDMA_256 SHIFTIN(4, RTW_TCR_MXDMA_MASK)
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#define RTW_TCR_MXDMA_512 SHIFTIN(5, RTW_TCR_MXDMA_MASK)
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#define RTW_TCR_MXDMA_1024 SHIFTIN(6, RTW_TCR_MXDMA_MASK)
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#define RTW_TCR_MXDMA_2048 SHIFTIN(7, RTW_TCR_MXDMA_MASK)
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/* disable 802.11 random backoff */
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#define RTW_TCR_DISCW __BIT(20)
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/* host lets RTL8180 append ICV to WEP packets */
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#define RTW_TCR_ICV __BIT(19)
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/* Loopback Test: disables TXI/TXQ outputs. */
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#define RTW_TCR_LBK_MASK __BITS(18,17)
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#define RTW_TCR_LBK_NORMAL SHIFTIN(0, RTW_TCR_LBK_MASK) /* normal ops */
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#define RTW_TCR_LBK_MAC SHIFTIN(1, RTW_TCR_LBK_MASK) /* MAC loopback */
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#define RTW_TCR_LBK_BBP SHIFTIN(2, RTW_TCR_LBK_MASK) /* baseband loop. */
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#define RTW_TCR_LBK_CONT SHIFTIN(3, RTW_TCR_LBK_MASK) /* continuous Tx */
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#define RTW_TCR_CRC __BIT(16) /* 0: RTL8180 appends CRC32
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* 1: host appends CRC32
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*
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* (I *think* this is right.
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* The docs have a mysterious
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* description in the
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* passive voice.)
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*/
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#define RTW_TCR_SRL_MASK __BITS(15,8) /* Short Retry Limit */
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#define RTW_TCR_LRL_MASK __BITS(7,0) /* Long Retry Limit */
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#define RTW_RCR 0x44 /* Receive Configuration Register, 32b */
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/* only do Early Rx on packets longer than 1536 bytes */
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#define RTW_RCR_ONLYERLPKT __BIT(31)
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/* enable carrier sense method 2 */
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#define RTW_RCR_ENCS2 __BIT(30)
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/* enable carrier sense method 1 */
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#define RTW_RCR_ENCS1 __BIT(29)
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#define RTW_RCR_ENMARP __BIT(28) /* enable MAC auto-reset PHY */
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/* Check BSSID/ToDS/FromDS: set "Link On" when received BSSID
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* matches RTW_BSSID and received ToDS/FromDS are appropriate
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* according to RTW_MSR_NETYPE.
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*/
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#define RTW_RCR_CBSSID __BIT(23)
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/* accept packets w/ PWRMGMT bit set */
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#define RTW_RCR_APWRMGT __BIT(22)
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/* when RTW_MSR_NETYPE == RTW_MSR_NETYPE_INFRA_OK, accept
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* broadcast/multicast packets whose 3rd address matches RTL8180's MAC.
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*/
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#define RTW_RCR_ADD3 __BIT(21)
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#define RTW_RCR_AMF __BIT(20) /* accept management frames */
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#define RTW_RCR_ACF __BIT(19) /* accept control frames */
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#define RTW_RCR_ADF __BIT(18) /* accept data frames */
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/* Rx FIFO Threshold: RTL8180 begins PCI transfer when this many data
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* bytes are received
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*/
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#define RTW_RCR_RXFTH_MASK __BITS(15,13)
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#define RTW_RCR_RXFTH_64 SHIFTIN(2, RTW_RCR_RXFTH_MASK)
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#define RTW_RCR_RXFTH_128 SHIFTIN(3, RTW_RCR_RXFTH_MASK)
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#define RTW_RCR_RXFTH_256 SHIFTIN(4, RTW_RCR_RXFTH_MASK)
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#define RTW_RCR_RXFTH_512 SHIFTIN(5, RTW_RCR_RXFTH_MASK)
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#define RTW_RCR_RXFTH_1024 SHIFTIN(6, RTW_RCR_RXFTH_MASK)
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#define RTW_RCR_RXFTH_WHOLE SHIFTIN(7, RTW_RCR_RXFTH_MASK)
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#define RTW_RCR_AICV __BIT(12)/* accept frames w/ ICV errors */
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/* Max DMA Burst Size per Rx DMA Burst */
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#define RTW_RCR_MXDMA_MASK __BITS(10,8)
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#define RTW_RCR_MXDMA_16 SHIFTIN(0, RTW_RCR_MXDMA_MASK)
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#define RTW_RCR_MXDMA_32 SHIFTIN(1, RTW_RCR_MXDMA_MASK)
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#define RTW_RCR_MXDMA_64 SHIFTIN(2, RTW_RCR_MXDMA_MASK)
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#define RTW_RCR_MXDMA_128 SHIFTIN(3, RTW_RCR_MXDMA_MASK)
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#define RTW_RCR_MXDMA_256 SHIFTIN(4, RTW_RCR_MXDMA_MASK)
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#define RTW_RCR_MXDMA_512 SHIFTIN(5, RTW_RCR_MXDMA_MASK)
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#define RTW_RCR_MXDMA_1024 SHIFTIN(6, RTW_RCR_MXDMA_MASK)
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#define RTW_RCR_MXDMA_UNLIMITED SHIFTIN(7, RTW_RCR_MXDMA_MASK)
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/* EEPROM type, read-only. 1: EEPROM is 93c56, 0: 93c46 */
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#define RTW_RCR_9356SEL __BIT(6)
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#define RTW_RCR_ACRC32 __BIT(5)/* accept frames w/ CRC32 errors */
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#define RTW_RCR_AB __BIT(3)/* accept broadcast frames */
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#define RTW_RCR_AM __BIT(2)/* accept multicast frames */
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/* accept physical match frames. XXX means PLCP header ok? */
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#define RTW_RCR_APM __BIT(1)
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#define RTW_RCR_AAP __BIT(0)/* accept frames w/ destination */
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/* Additional bits to set in monitor mode. */
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#define RTW_RCR_MONITOR ( \
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RTW_RCR_AAP | \
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RTW_RCR_ACF | \
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RTW_RCR_ACRC32 | \
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RTW_RCR_AICV | \
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0)
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/* The packet filter bits. */
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#define RTW_RCR_PKTFILTER_MASK (\
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RTW_RCR_AAP | \
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RTW_RCR_AB | \
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RTW_RCR_ACF | \
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RTW_RCR_ACRC32 | \
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RTW_RCR_ADD3 | \
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RTW_RCR_ADF | \
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RTW_RCR_AICV | \
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RTW_RCR_AM | \
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RTW_RCR_AMF | \
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RTW_RCR_APM | \
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RTW_RCR_APWRMGT | \
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0)
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/* Receive power-management frames and mgmt/ctrl/data frames. */
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#define RTW_RCR_PKTFILTER_DEFAULT ( \
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RTW_RCR_ADF | \
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RTW_RCR_AMF | \
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RTW_RCR_APM | \
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RTW_RCR_APWRMGT | \
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0)
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#define RTW_TINT 0x48 /* Timer Interrupt Register, 32b */
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#define RTW_TBDA 0x4c /* Transmit Beacon Descriptor Start Address,
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* 32b, 256-byte alignment
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*/
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#define RTW_9346CR 0x50 /* 93c46/93c56 Command Register, 8b */
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#define RTW_9346CR_EEM_MASK __BITS(7,6) /* Operating Mode */
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#define RTW_9346CR_EEM_NORMAL SHIFTIN(0, RTW_9346CR_EEM_MASK)
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/* Load the EEPROM. Reset registers to defaults.
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* Takes ~2ms. RTL8180 indicates completion with RTW_9346CR_EEM_NORMAL.
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* XXX RTL8180 only?
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*/
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#define RTW_9346CR_EEM_AUTOLOAD SHIFTIN(1, RTW_9346CR_EEM_MASK)
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/* Disable network & bus-master operations and enable
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* _EECS, _EESK, _EEDI, _EEDO.
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* XXX RTL8180 only?
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*/
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#define RTW_9346CR_EEM_PROGRAM SHIFTIN(2, RTW_9346CR_EEM_MASK)
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/* Enable RTW_CONFIG[0123] registers. */
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#define RTW_9346CR_EEM_CONFIG SHIFTIN(3, RTW_9346CR_EEM_MASK)
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/* EEPROM pin status/control in _EEM_CONFIG, _EEM_AUTOLOAD modes.
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* XXX RTL8180 only?
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*/
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#define RTW_9346CR_EECS __BIT(3)
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#define RTW_9346CR_EESK __BIT(2)
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#define RTW_9346CR_EEDI __BIT(1)
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#define RTW_9346CR_EEDO __BIT(0) /* read-only */
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#define RTW_CONFIG0 0x51 /* Configuration Register 0, 8b */
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#define RTW_CONFIG0_WEP40 __BIT(7)/* implements 40-bit WEP,
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* XXX RTL8180 only?
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*/
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#define RTW_CONFIG0_WEP104 __BIT(6)/* implements 104-bit WEP,
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* from EEPROM, read-only
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* XXX RTL8180 only?
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*/
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#define RTW_CONFIG0_LEDGPOEN __BIT(4)/* 1: RTW_PSR_LEDGPO[01] control
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* LED[01] pins.
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* 0: LED behavior defined by
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* RTW_CONFIG1_LEDS10_MASK
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* XXX RTL8180 only?
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*/
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/* auxiliary power is present, read-only */
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#define RTW_CONFIG0_AUXPWR __BIT(3)
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/* Geographic Location, read-only */
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#define RTW_CONFIG0_GL_MASK __BITS(1,0)
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/* _RTW_CONFIG0_GL_* is what the datasheet says, but RTW_CONFIG0_GL_*
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* work.
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*/
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#define _RTW_CONFIG0_GL_USA SHIFTIN(3, RTW_CONFIG0_GL_MASK)
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#define RTW_CONFIG0_GL_EUROPE SHIFTIN(2, RTW_CONFIG0_GL_MASK)
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#define RTW_CONFIG0_GL_JAPAN SHIFTIN(1, RTW_CONFIG0_GL_MASK)
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#define RTW_CONFIG0_GL_USA SHIFTIN(0, RTW_CONFIG0_GL_MASK)
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/* RTL8181 datasheet says RTW_CONFIG0_GL_JAPAN = 0. */
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#define RTW_CONFIG1 0x52 /* Configuration Register 1, 8b */
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/* LED configuration. From EEPROM. Read/write.
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*
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* Setting LED0 LED1
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* ------- ---- ----
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* RTW_CONFIG1_LEDS_ACT_INFRA Activity Infrastructure
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* RTW_CONFIG1_LEDS_ACT_LINK Activity Link
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* RTW_CONFIG1_LEDS_TX_RX Tx Rx
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* RTW_CONFIG1_LEDS_LINKACT_INFRA Link/Activity Infrastructure
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*/
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#define RTW_CONFIG1_LEDS_MASK __BITS(7,6)
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#define RTW_CONFIG1_LEDS_ACT_INFRA SHIFTIN(0, RTW_CONFIG1_LEDS_MASK)
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#define RTW_CONFIG1_LEDS_ACT_LINK SHIFTIN(1, RTW_CONFIG1_LEDS_MASK)
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#define RTW_CONFIG1_LEDS_TX_RX SHIFTIN(2, RTW_CONFIG1_LEDS_MASK)
|
|
#define RTW_CONFIG1_LEDS_LINKACT_INFRA SHIFTIN(3, RTW_CONFIG1_LEDS_MASK)
|
|
|
|
/* LWAKE Output Signal. Only applicable to Cardbus. Pulse width is 150ms.
|
|
*
|
|
* RTW_CONFIG1_LWACT
|
|
* 0 1
|
|
* RTW_CONFIG4_LWPTN 0 active high active low
|
|
* 1 positive pulse negative pulse
|
|
*/
|
|
#define RTW_CONFIG1_LWACT __BIT(4)
|
|
|
|
#define RTW_CONFIG1_MEMMAP __BIT(3)/* using PCI memory space, read-only */
|
|
#define RTW_CONFIG1_IOMAP __BIT(2)/* using PCI I/O space, read-only */
|
|
#define RTW_CONFIG1_VPD __BIT(1)/* if set, VPD from offsets
|
|
* 0x40-0x7f in EEPROM are at
|
|
* registers 0x60-0x67 of PCI
|
|
* Configuration Space (XXX huh?)
|
|
*/
|
|
#define RTW_CONFIG1_PMEN __BIT(0)/* Power Management Enable: TBD */
|
|
|
|
#define RTW_CONFIG2 0x53 /* Configuration Register 2, 8b */
|
|
#define RTW_CONFIG2_LCK __BIT(7)/* clocks are locked, read-only:
|
|
* Tx frequency & symbol clocks
|
|
* are derived from the same OSC
|
|
*/
|
|
#define RTW_CONFIG2_ANT __BIT(6) /* diversity enabled, read-only */
|
|
#define RTW_CONFIG2_DPS __BIT(3) /* Descriptor Polling State: enable
|
|
* test mode.
|
|
*/
|
|
#define RTW_CONFIG2_PAPESIGN __BIT(2) /* TBD, from EEPROM */
|
|
#define RTW_CONFIG2_PAPETIME_MASK __BITS(1,0) /* TBD, from EEPROM */
|
|
|
|
#define RTW_ANAPARM 0x54 /* Analog parameter, 32b */
|
|
#define RTW_ANAPARM_RFPOW0_MASK __BITS(30,28) /* undocumented bits
|
|
* which appear to
|
|
* control the power
|
|
* state of the RF
|
|
* components
|
|
*/
|
|
#define RTW_ANAPARM_RFPOW_MASK \
|
|
(RTW_ANAPARM_RFPOW0_MASK|RTW_ANAPARM_RFPOW1_MASK)
|
|
|
|
#define RTW_ANAPARM_TXDACOFF __BIT(27) /* 1: disable Tx DAC,
|
|
* 0: enable
|
|
*/
|
|
#define RTW_ANAPARM_RFPOW1_MASK __BITS(26,20) /* undocumented bits
|
|
* which appear to
|
|
* control the power
|
|
* state of the RF
|
|
* components
|
|
*/
|
|
|
|
/*
|
|
* Maxim On/Sleep/Off control
|
|
*/
|
|
#define RTW_ANAPARM_RFPOW_MAXIM_ON SHIFTIN(0x8, RTW_ANAPARM_RFPOW1_MASK)
|
|
|
|
/* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
|
|
#define RTW_ANAPARM_RFPOW_MAXIM_SLEEP SHIFTIN(0x378, RTW_ANAPARM_RFPOW1_MASK)
|
|
|
|
/* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
|
|
#define RTW_ANAPARM_RFPOW_MAXIM_OFF SHIFTIN(0x379, RTW_ANAPARM_RFPOW1_MASK)
|
|
|
|
/*
|
|
* RFMD On/Sleep/Off control
|
|
*/
|
|
#define RTW_ANAPARM_RFPOW_RFMD_ON SHIFTIN(0x408, RTW_ANAPARM_RFPOW1_MASK)
|
|
|
|
/* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
|
|
#define RTW_ANAPARM_RFPOW_RFMD_SLEEP SHIFTIN(0x378, RTW_ANAPARM_RFPOW1_MASK)
|
|
|
|
/* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
|
|
#define RTW_ANAPARM_RFPOW_RFMD_OFF SHIFTIN(0x379, RTW_ANAPARM_RFPOW1_MASK)
|
|
|
|
/*
|
|
* Philips On/Sleep/Off control
|
|
*/
|
|
#define RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON \
|
|
SHIFTIN(0x328, RTW_ANAPARM_RFPOW1_MASK)
|
|
#define RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON \
|
|
SHIFTIN(0x008, RTW_ANAPARM_RFPOW1_MASK)
|
|
|
|
/* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
|
|
#define RTW_ANAPARM_RFPOW_PHILIPS_SLEEP\
|
|
SHIFTIN(0x378, RTW_ANAPARM_RFPOW1_MASK)
|
|
|
|
/* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
|
|
#define RTW_ANAPARM_RFPOW_PHILIPS_OFF\
|
|
SHIFTIN(0x379, RTW_ANAPARM_RFPOW1_MASK)
|
|
|
|
#define RTW_ANAPARM_RFPOW_PHILIPS_ON SHIFTIN(0x328, RTW_ANAPARM_RFPOW1_MASK)
|
|
|
|
#define RTW_ANAPARM_CARDSP_MASK __BITS(19,0) /* undocumented
|
|
* card-specific
|
|
* bits from the
|
|
* EEPROM.
|
|
*/
|
|
|
|
#define RTW_MSR 0x58 /* Media Status Register, 8b */
|
|
/* Network Type and Link Status */
|
|
#define RTW_MSR_NETYPE_MASK __BITS(3,2)
|
|
/* AP, XXX RTL8181 only? */
|
|
#define RTW_MSR_NETYPE_AP_OK SHIFTIN(3, RTW_MSR_NETYPE_MASK)
|
|
/* infrastructure link ok */
|
|
#define RTW_MSR_NETYPE_INFRA_OK SHIFTIN(2, RTW_MSR_NETYPE_MASK)
|
|
/* ad-hoc link ok */
|
|
#define RTW_MSR_NETYPE_ADHOC_OK SHIFTIN(1, RTW_MSR_NETYPE_MASK)
|
|
/* no link */
|
|
#define RTW_MSR_NETYPE_NOLINK SHIFTIN(0, RTW_MSR_NETYPE_MASK)
|
|
|
|
#define RTW_CONFIG3 0x59 /* Configuration Register 3, 8b */
|
|
#define RTW_CONFIG3_GNTSEL __BIT(7) /* Grant Select, read-only */
|
|
#define RTW_CONFIG3_PARMEN __BIT(6) /* Set RTW_CONFIG3_PARMEN and
|
|
* RTW_9346CR_EEM_CONFIG to
|
|
* allow RTW_ANAPARM writes.
|
|
*/
|
|
#define RTW_CONFIG3_MAGIC __BIT(5)/* Valid when RTW_CONFIG1_PMEN is
|
|
* set. If set, RTL8180 wakes up
|
|
* OS when Magic Packet is Rx'd.
|
|
*/
|
|
#define RTW_CONFIG3_CARDBEN __BIT(3)/* Cardbus-related registers
|
|
* and functions are enabled,
|
|
* read-only. XXX RTL8180 only.
|
|
*/
|
|
#define RTW_CONFIG3_CLKRUNEN __BIT(2)/* CLKRUN enabled, read-only.
|
|
* XXX RTL8180 only.
|
|
*/
|
|
#define RTW_CONFIG3_FUNCREGEN __BIT(1)/* Function Registers Enabled,
|
|
* read-only. XXX RTL8180 only.
|
|
*/
|
|
#define RTW_CONFIG3_FBTBEN __BIT(0)/* Fast back-to-back enabled,
|
|
* read-only.
|
|
*/
|
|
#define RTW_CONFIG4 0x5A /* Configuration Register 4, 8b */
|
|
#define RTW_CONFIG4_VCOPDN __BIT(7)/* VCO Power Down
|
|
* 0: normal operation
|
|
* (power-on default)
|
|
* 1: power-down VCO, RF front-end,
|
|
* and most RTL8180 components.
|
|
*/
|
|
#define RTW_CONFIG4_PWROFF __BIT(6)/* Power Off
|
|
* 0: normal operation
|
|
* (power-on default)
|
|
* 1: power-down RF front-end,
|
|
* and most RTL8180 components,
|
|
* but leave VCO on.
|
|
*
|
|
* XXX RFMD front-end only?
|
|
*/
|
|
#define RTW_CONFIG4_PWRMGT __BIT(5)/* Power Management
|
|
* 0: normal operation
|
|
* (power-on default)
|
|
* 1: set Tx packet's PWRMGMT bit.
|
|
*/
|
|
#define RTW_CONFIG4_LWPME __BIT(4)/* LANWAKE vs. PMEB: Cardbus-only
|
|
* 0: LWAKE & PMEB asserted
|
|
* simultaneously
|
|
* 1: LWAKE asserted only if
|
|
* both PMEB is asserted and
|
|
* ISOLATEB is low.
|
|
* XXX RTL8180 only.
|
|
*/
|
|
#define RTW_CONFIG4_LWPTN __BIT(2)/* see RTW_CONFIG1_LWACT
|
|
* XXX RTL8180 only.
|
|
*/
|
|
/* Radio Front-End Programming Method */
|
|
#define RTW_CONFIG4_RFTYPE_MASK __BITS(1,0)
|
|
#define RTW_CONFIG4_RFTYPE_INTERSIL SHIFTIN(1, RTW_CONFIG4_RFTYPE_MASK)
|
|
#define RTW_CONFIG4_RFTYPE_RFMD SHIFTIN(2, RTW_CONFIG4_RFTYPE_MASK)
|
|
#define RTW_CONFIG4_RFTYPE_PHILIPS SHIFTIN(3, RTW_CONFIG4_RFTYPE_MASK)
|
|
|
|
#define RTW_TESTR 0x5B /* TEST mode register, 8b */
|
|
|
|
#define RTW_PSR 0x5e /* Page Select Register, 8b */
|
|
#define RTW_PSR_GPO __BIT(7)/* Control/status of pin 52. */
|
|
#define RTW_PSR_GPI __BIT(6)/* Status of pin 64. */
|
|
#define RTW_PSR_LEDGPO1 __BIT(5)/* Status/control of LED1 pin if
|
|
* RTW_CONFIG0_LEDGPOEN is set.
|
|
*/
|
|
#define RTW_PSR_LEDGPO0 __BIT(4)/* Status/control of LED0 pin if
|
|
* RTW_CONFIG0_LEDGPOEN is set.
|
|
*/
|
|
#define RTW_PSR_UWF __BIT(1)/* Enable Unicast Wakeup Frame */
|
|
#define RTW_PSR_PSEN __BIT(0)/* 1: page 1, 0: page 0 */
|
|
|
|
#define RTW_SCR 0x5f /* Security Configuration Register, 8b */
|
|
#define RTW_SCR_KM_MASK __BITS(5,4) /* Key Mode */
|
|
#define RTW_SCR_KM_WEP104 SHIFTIN(1, RTW_SCR_KM_MASK)
|
|
#define RTW_SCR_KM_WEP40 SHIFTIN(0, RTW_SCR_KM_MASK)
|
|
#define RTW_SCR_TXSECON __BIT(1)/* Enable Tx WEP. Invalid if
|
|
* neither RTW_CONFIG0_WEP40 nor
|
|
* RTW_CONFIG0_WEP104 is set.
|
|
*/
|
|
#define RTW_SCR_RXSECON __BIT(0)/* Enable Rx WEP. Invalid if
|
|
* neither RTW_CONFIG0_WEP40 nor
|
|
* RTW_CONFIG0_WEP104 is set.
|
|
*/
|
|
|
|
#define RTW_BCNITV 0x70 /* Beacon Interval Register, 16b */
|
|
#define RTW_BCNITV_BCNITV_MASK __BITS(9,0) /* TU between TBTT, written
|
|
* by host.
|
|
*/
|
|
#define RTW_ATIMWND 0x72 /* ATIM Window Register, 16b */
|
|
#define RTW_ATIMWND_ATIMWND __BITS(9,0) /* ATIM Window length in TU,
|
|
* written by host.
|
|
*/
|
|
|
|
#define RTW_BINTRITV 0x74 /* Beacon Interrupt Interval Register, 16b */
|
|
#define RTW_BINTRITV_BINTRITV __BITS(9,0) /* RTL8180 wakes host with
|
|
* RTW_INTR_BCNINT at BINTRITV
|
|
* microseconds before TBTT
|
|
*/
|
|
#define RTW_ATIMTRITV 0x76 /* ATIM Interrupt Interval Register, 16b */
|
|
#define RTW_ATIMTRITV_ATIMTRITV __BITS(9,0) /* RTL8180 wakes host with
|
|
* RTW_INTR_ATIMINT at ATIMTRITV
|
|
* microseconds before end of
|
|
* ATIM Window
|
|
*/
|
|
|
|
#define RTW_PHYDELAY 0x78 /* PHY Delay Register, 8b */
|
|
#define RTW_PHYDELAY_REVC_MAGIC __BIT(3) /* Rev. C magic from reference
|
|
* driver
|
|
*/
|
|
#define RTW_PHYDELAY_PHYDELAY __BITS(2,0) /* microsecond Tx delay between
|
|
* MAC and RF front-end
|
|
*/
|
|
#define RTW_CRCOUNT 0x79 /* Carrier Sense Counter, 8b */
|
|
#define RTW_CRCOUNT_MAGIC 0x4c
|
|
|
|
#define RTW_CRC16ERR 0x7a /* CRC16 error count, 16b, XXX RTL8181 only? */
|
|
|
|
#define RTW_BB 0x7c /* Baseband interface, 32b */
|
|
/* used for writing RTL8180's integrated baseband processor */
|
|
#define RTW_BB_RD_MASK __BITS(23,16) /* data to read */
|
|
#define RTW_BB_WR_MASK __BITS(15,8) /* data to write */
|
|
#define RTW_BB_WREN __BIT(7) /* write enable */
|
|
#define RTW_BB_ADDR_MASK __BITS(6,0) /* address */
|
|
|
|
#define RTW_PHYADDR 0x7c /* Address register for PHY interface, 8b */
|
|
#define RTW_PHYDATAW 0x7d /* Write data to PHY, 8b, write-only */
|
|
#define RTW_PHYDATAR 0x7e /* Read data from PHY, 8b (?), read-only */
|
|
|
|
#define RTW_PHYCFG 0x80 /* PHY Configuration Register, 32b */
|
|
#define RTW_PHYCFG_MAC_POLL __BIT(31) /* if !RTW_PHYCFG_HST,
|
|
* host sets. MAC clears
|
|
* after banging bits.
|
|
*/
|
|
#define RTW_PHYCFG_HST __BIT(30) /* 1: host bangs bits
|
|
* 0: MAC bangs bits
|
|
*/
|
|
#define RTW_PHYCFG_MAC_RFTYPE_MASK __BITS(29,28)
|
|
#define RTW_PHYCFG_MAC_RFTYPE_INTERSIL SHIFTIN(0, RTW_PHYCFG_MAC_RFTYPE_MASK)
|
|
#define RTW_PHYCFG_MAC_RFTYPE_RFMD SHIFTIN(1, RTW_PHYCFG_MAC_RFTYPE_MASK)
|
|
#define RTW_PHYCFG_MAC_RFTYPE_GCT RTW_PHYCFG_MAC_RFTYPE_RFMD
|
|
#define RTW_PHYCFG_MAC_RFTYPE_PHILIPS SHIFTIN(3, RTW_PHYCFG_MAC_RFTYPE_MASK)
|
|
#define RTW_PHYCFG_MAC_PHILIPS_ADDR_MASK __BITS(27,24)
|
|
#define RTW_PHYCFG_MAC_PHILIPS_DATA_MASK __BITS(23,0)
|
|
#define RTW_PHYCFG_MAC_MAXIM_LODATA_MASK __BITS(27,24)
|
|
#define RTW_PHYCFG_MAC_MAXIM_ADDR_MASK __BITS(11,8)
|
|
#define RTW_PHYCFG_MAC_MAXIM_HIDATA_MASK __BITS(7,0)
|
|
#define RTW_PHYCFG_HST_EN __BIT(2)
|
|
#define RTW_PHYCFG_HST_CLK __BIT(1)
|
|
#define RTW_PHYCFG_HST_DATA __BIT(0)
|
|
|
|
#define RTW_MAXIM_HIDATA_MASK __BITS(11,4)
|
|
#define RTW_MAXIM_LODATA_MASK __BITS(3,0)
|
|
|
|
/**
|
|
** 0x84 - 0xD3, page 1, selected when RTW_PSR[PSEN] == 1.
|
|
**/
|
|
|
|
#define RTW_WAKEUP0L 0x84 /* Power Management Wakeup Frame */
|
|
#define RTW_WAKEUP0H 0x88 /* 32b */
|
|
|
|
#define RTW_WAKEUP1L 0x8c
|
|
#define RTW_WAKEUP1H 0x90
|
|
|
|
#define RTW_WAKEUP2LL 0x94
|
|
#define RTW_WAKEUP2LH 0x98
|
|
|
|
#define RTW_WAKEUP2HL 0x9c
|
|
#define RTW_WAKEUP2HH 0xa0
|
|
|
|
#define RTW_WAKEUP3LL 0xa4
|
|
#define RTW_WAKEUP3LH 0xa8
|
|
|
|
#define RTW_WAKEUP3HL 0xac
|
|
#define RTW_WAKEUP3HH 0xb0
|
|
|
|
#define RTW_WAKEUP4LL 0xb4
|
|
#define RTW_WAKEUP4LH 0xb8
|
|
|
|
#define RTW_WAKEUP4HL 0xbc
|
|
#define RTW_WAKEUP4HH 0xc0
|
|
|
|
#define RTW_CRC0 0xc4 /* CRC of wakeup frame 0, 16b */
|
|
#define RTW_CRC1 0xc6 /* CRC of wakeup frame 1, 16b */
|
|
#define RTW_CRC2 0xc8 /* CRC of wakeup frame 2, 16b */
|
|
#define RTW_CRC3 0xca /* CRC of wakeup frame 3, 16b */
|
|
#define RTW_CRC4 0xcc /* CRC of wakeup frame 4, 16b */
|
|
|
|
/**
|
|
** 0x84 - 0xD3, page 0, selected when RTW_PSR[PSEN] == 0.
|
|
**/
|
|
|
|
/* Default Key Registers, each 128b
|
|
*
|
|
* If RTW_SCR_KM_WEP104, 104 lsb are the key.
|
|
* If RTW_SCR_KM_WEP40, 40 lsb are the key.
|
|
*/
|
|
#define RTW_DK0 0x90 /* Default Key 0 Register, 128b */
|
|
#define RTW_DK1 0xa0 /* Default Key 1 Register, 128b */
|
|
#define RTW_DK2 0xb0 /* Default Key 2 Register, 128b */
|
|
#define RTW_DK3 0xc0 /* Default Key 3 Register, 128b */
|
|
|
|
#define RTW_CONFIG5 0xd8 /* Configuration Register 5, 8b */
|
|
#define RTW_CONFIG5_TXFIFOOK __BIT(7)/* Tx FIFO self-test pass, read-only */
|
|
#define RTW_CONFIG5_RXFIFOOK __BIT(6)/* Rx FIFO self-test pass, read-only */
|
|
#define RTW_CONFIG5_CALON __BIT(5)/* 1: start calibration cycle
|
|
* and raise AGCRESET pin.
|
|
* 0: lower AGCRESET pin
|
|
*/
|
|
#define RTW_CONFIG5_EACPI __BIT(2)/* Enable ACPI Wake up, default 0 */
|
|
#define RTW_CONFIG5_LANWAKE __BIT(1)/* Enable LAN Wake signal,
|
|
* from EEPROM
|
|
*/
|
|
#define RTW_CONFIG5_PMESTS __BIT(0)/* 1: both software & PCI Reset
|
|
* reset PME_Status
|
|
* 0: only software resets PME_Status
|
|
*
|
|
* From EEPROM.
|
|
*/
|
|
|
|
#define RTW_TPPOLL 0xd9 /* Transmit Priority Polling Register, 8b,
|
|
* write-only.
|
|
*/
|
|
#define RTW_TPPOLL_BQ __BIT(7)/* RTL8180 clears to notify host of a beacon
|
|
* Tx. Host writes have no effect.
|
|
*/
|
|
#define RTW_TPPOLL_HPQ __BIT(6)/* Host writes 1 to notify RTL8180 of
|
|
* high-priority Tx packets, RTL8180 clears
|
|
* to after high-priority Tx is complete.
|
|
*/
|
|
#define RTW_TPPOLL_NPQ __BIT(5)/* If RTW_CONFIG2_DPS is set,
|
|
* host writes 1 to notify RTL8180 of
|
|
* normal-priority Tx packets, RTL8180 clears
|
|
* after normal-priority Tx is complete.
|
|
*
|
|
* If RTW_CONFIG2_DPS is clear, host writes
|
|
* have no effect. RTL8180 clears after
|
|
* normal-priority Tx is complete.
|
|
*/
|
|
#define RTW_TPPOLL_LPQ __BIT(4)/* Host writes 1 to notify RTL8180 of
|
|
* low-priority Tx packets, RTL8180 clears
|
|
* after low-priority Tx is complete.
|
|
*/
|
|
#define RTW_TPPOLL_SBQ __BIT(3)/* Host writes 1 to tell RTL8180 to
|
|
* stop beacon DMA. This bit is invalid
|
|
* when RTW_CONFIG2_DPS is set.
|
|
*/
|
|
#define RTW_TPPOLL_SHPQ __BIT(2)/* Host writes 1 to tell RTL8180 to
|
|
* stop high-priority DMA.
|
|
*/
|
|
#define RTW_TPPOLL_SNPQ __BIT(1)/* Host writes 1 to tell RTL8180 to
|
|
* stop normal-priority DMA. This bit is invalid
|
|
* when RTW_CONFIG2_DPS is set.
|
|
*/
|
|
#define RTW_TPPOLL_SLPQ __BIT(0)/* Host writes 1 to tell RTL8180 to
|
|
* stop low-priority DMA.
|
|
*/
|
|
|
|
/* Start all queues. */
|
|
#define RTW_TPPOLL_ALL (RTW_TPPOLL_BQ | RTW_TPPOLL_HPQ | \
|
|
RTW_TPPOLL_NPQ | RTW_TPPOLL_LPQ)
|
|
/* Check all queues' activity. */
|
|
#define RTW_TPPOLL_ACTIVE RTW_TPPOLL_ALL
|
|
/* Stop all queues. */
|
|
#define RTW_TPPOLL_SALL (RTW_TPPOLL_SBQ | RTW_TPPOLL_SHPQ | \
|
|
RTW_TPPOLL_SNPQ | RTW_TPPOLL_SLPQ)
|
|
|
|
#define RTW_CWR 0xdc /* Contention Window Register, 16b, read-only */
|
|
/* Contention Window: indicates number of contention windows before Tx
|
|
*/
|
|
#define RTW_CWR_CW __BITS(9,0)
|
|
|
|
/* Retry Count Register, 16b, read-only */
|
|
#define RTW_RETRYCTR 0xde
|
|
/* Retry Count: indicates number of retries after Tx */
|
|
#define RTW_RETRYCTR_RETRYCT __BITS(7,0)
|
|
|
|
#define RTW_RDSAR 0xe4 /* Receive descriptor Start Address Register,
|
|
* 32b, 256-byte alignment.
|
|
*/
|
|
/* Function Event Register, 32b, Cardbus only. Only valid when
|
|
* both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set.
|
|
*/
|
|
#define RTW_FER 0xf0
|
|
#define RTW_FER_INTR __BIT(15) /* set when RTW_FFER_INTR is set */
|
|
#define RTW_FER_GWAKE __BIT(4) /* General Wakeup */
|
|
/* Function Event Mask Register, 32b, Cardbus only. Only valid when
|
|
* both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set.
|
|
*/
|
|
#define RTW_FEMR 0xf4
|
|
#define RTW_FEMR_INTR __BIT(15) /* set when RTW_FFER_INTR is set */
|
|
#define RTW_FEMR_WKUP __BIT(14) /* Wakeup Mask */
|
|
#define RTW_FEMR_GWAKE __BIT(4) /* General Wakeup */
|
|
/* Function Present State Register, 32b, read-only, Cardbus only.
|
|
* Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN
|
|
* are set.
|
|
*/
|
|
#define RTW_FPSR 0xf8
|
|
#define RTW_FPSR_INTR __BIT(15) /* TBD */
|
|
#define RTW_FPSR_GWAKE __BIT(4) /* General Wakeup: TBD */
|
|
/* Function Force Event Register, 32b, write-only, Cardbus only.
|
|
* Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN
|
|
* are set.
|
|
*/
|
|
#define RTW_FFER 0xfc
|
|
#define RTW_FFER_INTR __BIT(15) /* TBD */
|
|
#define RTW_FFER_GWAKE __BIT(4) /* General Wakeup: TBD */
|
|
|
|
/* Serial EEPROM offsets */
|
|
#define RTW_SR_ID 0x00 /* 16b */
|
|
#define RTW_SR_VID 0x02 /* 16b */
|
|
#define RTW_SR_DID 0x04 /* 16b */
|
|
#define RTW_SR_SVID 0x06 /* 16b */
|
|
#define RTW_SR_SMID 0x08 /* 16b */
|
|
#define RTW_SR_MNGNT 0x0a
|
|
#define RTW_SR_MXLAT 0x0b
|
|
#define RTW_SR_RFCHIPID 0x0c
|
|
#define RTW_SR_CONFIG3 0x0d
|
|
#define RTW_SR_MAC 0x0e /* 6 bytes */
|
|
#define RTW_SR_CONFIG0 0x14
|
|
#define RTW_SR_CONFIG1 0x15
|
|
#define RTW_SR_PMC 0x16 /* Power Management Capabilities, 16b */
|
|
#define RTW_SR_CONFIG2 0x18
|
|
#define RTW_SR_CONFIG4 0x19
|
|
#define RTW_SR_ANAPARM 0x1a /* Analog Parameters, 32b */
|
|
#define RTW_SR_TESTR 0x1e
|
|
#define RTW_SR_CONFIG5 0x1f
|
|
#define RTW_SR_TXPOWER1 0x20
|
|
#define RTW_SR_TXPOWER2 0x21
|
|
#define RTW_SR_TXPOWER3 0x22
|
|
#define RTW_SR_TXPOWER4 0x23
|
|
#define RTW_SR_TXPOWER5 0x24
|
|
#define RTW_SR_TXPOWER6 0x25
|
|
#define RTW_SR_TXPOWER7 0x26
|
|
#define RTW_SR_TXPOWER8 0x27
|
|
#define RTW_SR_TXPOWER9 0x28
|
|
#define RTW_SR_TXPOWER10 0x29
|
|
#define RTW_SR_TXPOWER11 0x2a
|
|
#define RTW_SR_TXPOWER12 0x2b
|
|
#define RTW_SR_TXPOWER13 0x2c
|
|
#define RTW_SR_TXPOWER14 0x2d
|
|
#define RTW_SR_CHANNELPLAN 0x2e /* bitmap of channels to scan */
|
|
#define RTW_SR_ENERGYDETTHR 0x2f /* energy-detect threshold */
|
|
#define RTW_SR_ENERGYDETTHR_DEFAULT 0x0c /* use this if old SROM */
|
|
#define RTW_SR_CISPOINTER 0x30 /* 16b */
|
|
#define RTW_SR_RFPARM 0x32 /* RF-specific parameter */
|
|
#define RTW_SR_RFPARM_DIGPHY __BIT(0) /* 1: digital PHY */
|
|
#define RTW_SR_RFPARM_DFLANTB __BIT(1) /* 1: antenna B is default */
|
|
#define RTW_SR_RFPARM_CS_MASK __BITS(2,3) /* carrier-sense type */
|
|
#define RTW_SR_VERSION 0x3c /* EEPROM content version, 16b */
|
|
#define RTW_SR_CRC 0x3e /* EEPROM content CRC, 16b */
|
|
#define RTW_SR_VPD 0x40 /* Vital Product Data, 64 bytes */
|
|
#define RTW_SR_CIS 0x80 /* CIS Data, 93c56 only, 128 bytes*/
|
|
|
|
/*
|
|
* RTL8180 Transmit/Receive Descriptors
|
|
*/
|
|
|
|
/* the first descriptor in each ring must be on a 256-byte boundary */
|
|
#define RTW_DESC_ALIGNMENT 256
|
|
|
|
/* Tx descriptor */
|
|
struct rtw_txdesc {
|
|
uint32_t td_ctl0;
|
|
uint32_t td_ctl1;
|
|
uint32_t td_buf;
|
|
uint32_t td_len;
|
|
uint32_t td_next;
|
|
uint32_t td_rsvd[3];
|
|
};
|
|
|
|
#define td_stat td_ctl0
|
|
|
|
#define RTW_TXCTL0_OWN __BIT(31) /* 1: ready to Tx */
|
|
#define RTW_TXCTL0_RSVD0 __BIT(30) /* reserved */
|
|
#define RTW_TXCTL0_FS __BIT(29) /* first segment */
|
|
#define RTW_TXCTL0_LS __BIT(28) /* last segment */
|
|
|
|
#define RTW_TXCTL0_RATE_MASK __BITS(27,24) /* Tx rate */
|
|
#define RTW_TXCTL0_RATE_1MBPS SHIFTIN(0, RTW_TXCTL0_RATE_MASK)
|
|
#define RTW_TXCTL0_RATE_2MBPS SHIFTIN(1, RTW_TXCTL0_RATE_MASK)
|
|
#define RTW_TXCTL0_RATE_5MBPS SHIFTIN(2, RTW_TXCTL0_RATE_MASK)
|
|
#define RTW_TXCTL0_RATE_11MBPS SHIFTIN(3, RTW_TXCTL0_RATE_MASK)
|
|
|
|
#define RTW_TXCTL0_RTSEN __BIT(23) /* RTS Enable */
|
|
|
|
#define RTW_TXCTL0_RTSRATE_MASK __BITS(22,19) /* Tx rate */
|
|
#define RTW_TXCTL0_RTSRATE_1MBPS SHIFTIN(0, RTW_TXCTL0_RTSRATE_MASK)
|
|
#define RTW_TXCTL0_RTSRATE_2MBPS SHIFTIN(1, RTW_TXCTL0_RTSRATE_MASK)
|
|
#define RTW_TXCTL0_RTSRATE_5MBPS SHIFTIN(2, RTW_TXCTL0_RTSRATE_MASK)
|
|
#define RTW_TXCTL0_RTSRATE_11MBPS SHIFTIN(3, RTW_TXCTL0_RTSRATE_MASK)
|
|
|
|
#define RTW_TXCTL0_BEACON __BIT(18) /* packet is a beacon */
|
|
#define RTW_TXCTL0_MOREFRAG __BIT(17) /* another fragment
|
|
* follows
|
|
*/
|
|
/* add short PLCP preamble and header */
|
|
#define RTW_TXCTL0_SPLCP __BIT(16)
|
|
#define RTW_TXCTL0_KEYID_MASK __BITS(15,14) /* default key id */
|
|
#define RTW_TXCTL0_RSVD1_MASK __BITS(13,12) /* reserved */
|
|
#define RTW_TXCTL0_TPKTSIZE_MASK __BITS(11,0) /* Tx packet size
|
|
* in bytes
|
|
*/
|
|
|
|
#define RTW_TXSTAT_OWN RTW_TXCTL0_OWN
|
|
#define RTW_TXSTAT_RSVD0 RTW_TXCTL0_RSVD0
|
|
#define RTW_TXSTAT_FS RTW_TXCTL0_FS
|
|
#define RTW_TXSTAT_LS RTW_TXCTL0_LS
|
|
#define RTW_TXSTAT_RSVD1_MASK __BITS(27,16)
|
|
#define RTW_TXSTAT_TOK __BIT(15)
|
|
#define RTW_TXSTAT_RTSRETRY_MASK __BITS(14,8) /* RTS retry count */
|
|
#define RTW_TXSTAT_DRC_MASK __BITS(7,0) /* Data retry count */
|
|
|
|
#define RTW_TXCTL1_LENGEXT __BIT(31) /* supplements _LENGTH
|
|
* in packets sent 5.5Mb/s or
|
|
* faster
|
|
*/
|
|
#define RTW_TXCTL1_LENGTH_MASK __BITS(30,16) /* PLCP length (microseconds) */
|
|
#define RTW_TXCTL1_RTSDUR_MASK __BITS(15,0) /* RTS Duration
|
|
* (microseconds)
|
|
*/
|
|
|
|
#define RTW_TXLEN_LENGTH_MASK __BITS(11,0) /* Tx buffer length in bytes */
|
|
|
|
/* Rx descriptor */
|
|
struct rtw_rxdesc {
|
|
uint32_t rd_ctl;
|
|
uint32_t rd_rsvd0;
|
|
uint32_t rd_buf;
|
|
uint32_t rd_rsvd1;
|
|
};
|
|
|
|
#define rd_stat rd_ctl
|
|
#define rd_rssi rd_rsvd0
|
|
#define rd_tsftl rd_buf /* valid only when RTW_RXSTAT_LS is set */
|
|
#define rd_tsfth rd_rsvd1 /* valid only when RTW_RXSTAT_LS is set */
|
|
|
|
#define RTW_RXCTL_OWN __BIT(31) /* 1: owned by NIC */
|
|
#define RTW_RXCTL_EOR __BIT(30) /* end of ring */
|
|
#define RTW_RXCTL_FS __BIT(29) /* first segment */
|
|
#define RTW_RXCTL_LS __BIT(28) /* last segment */
|
|
#define RTW_RXCTL_RSVD0_MASK __BITS(29,12) /* reserved */
|
|
#define RTW_RXCTL_LENGTH_MASK __BITS(11,0) /* Rx buffer length */
|
|
|
|
#define RTW_RXSTAT_OWN RTW_RXCTL_OWN
|
|
#define RTW_RXSTAT_EOR RTW_RXCTL_EOR
|
|
#define RTW_RXSTAT_FS RTW_RXCTL_FS /* first segment */
|
|
#define RTW_RXSTAT_LS RTW_RXCTL_LS /* last segment */
|
|
#define RTW_RXSTAT_DMAFAIL __BIT(27) /* DMA failure on this pkt */
|
|
#define RTW_RXSTAT_BOVF __BIT(26) /* buffer overflow XXX means
|
|
* FIFO exhausted?
|
|
*/
|
|
#define RTW_RXSTAT_SPLCP __BIT(25) /* Rx'd with short preamble
|
|
* and PLCP header
|
|
*/
|
|
#define RTW_RXSTAT_RSVD1 __BIT(24) /* reserved */
|
|
#define RTW_RXSTAT_RATE_MASK __BITS(23,20) /* Rx rate */
|
|
#define RTW_RXSTAT_RATE_1MBPS SHIFTIN(0, RTW_RXSTAT_RATE_MASK)
|
|
#define RTW_RXSTAT_RATE_2MBPS SHIFTIN(1, RTW_RXSTAT_RATE_MASK)
|
|
#define RTW_RXSTAT_RATE_5MBPS SHIFTIN(2, RTW_RXSTAT_RATE_MASK)
|
|
#define RTW_RXSTAT_RATE_11MBPS SHIFTIN(3, RTW_RXSTAT_RATE_MASK)
|
|
#define RTW_RXSTAT_MIC __BIT(19) /* XXX from reference driver */
|
|
#define RTW_RXSTAT_MAR __BIT(18) /* is multicast */
|
|
#define RTW_RXSTAT_PAR __BIT(17) /* matches RTL8180's MAC */
|
|
#define RTW_RXSTAT_BAR __BIT(16) /* is broadcast */
|
|
#define RTW_RXSTAT_RES __BIT(15) /* error summary. valid when
|
|
* RTW_RXSTAT_LS set. indicates
|
|
* that either RTW_RXSTAT_CRC32
|
|
* or RTW_RXSTAT_ICV is set.
|
|
*/
|
|
#define RTW_RXSTAT_PWRMGT __BIT(14) /* 802.11 PWRMGMT bit is set */
|
|
#define RTW_RXSTAT_CRC16 __BIT(14) /* XXX CRC16 error, from
|
|
* reference driver
|
|
*/
|
|
#define RTW_RXSTAT_CRC32 __BIT(13) /* CRC32 error */
|
|
#define RTW_RXSTAT_ICV __BIT(12) /* ICV error */
|
|
#define RTW_RXSTAT_LENGTH_MASK __BITS(11,0) /* frame length, including
|
|
* CRC32
|
|
*/
|
|
|
|
/* Convenient status conjunction. */
|
|
#define RTW_RXSTAT_ONESEG (RTW_RXSTAT_FS|RTW_RXSTAT_LS)
|
|
/* Convenient status disjunctions. */
|
|
#define RTW_RXSTAT_IOERROR (RTW_RXSTAT_DMAFAIL|RTW_RXSTAT_BOVF)
|
|
#define RTW_RXSTAT_DEBUG (RTW_RXSTAT_SPLCP|RTW_RXSTAT_MAR|\
|
|
RTW_RXSTAT_PAR|RTW_RXSTAT_BAR|\
|
|
RTW_RXSTAT_PWRMGT|RTW_RXSTAT_CRC32|\
|
|
RTW_RXSTAT_ICV)
|
|
|
|
|
|
#define RTW_RXRSSI_VLAN __BITS(31,16) /* XXX from reference driver */
|
|
/* for Philips RF front-ends */
|
|
#define RTW_RXRSSI_RSSI __BITS(15,8) /* RF energy at the PHY */
|
|
/* for RF front-ends by Intersil, Maxim, RFMD */
|
|
#define RTW_RXRSSI_IMR_RSSI __BITS(15,9) /* RF energy at the PHY */
|
|
#define RTW_RXRSSI_IMR_LNA __BIT(8) /* 1: LNA activated */
|
|
#define RTW_RXRSSI_SQ __BITS(7,0) /* Barker code-lock quality */
|
|
|
|
#define RTW_READ8(regs, ofs) \
|
|
bus_space_read_1((regs)->r_bt, (regs)->r_bh, (ofs))
|
|
|
|
#define RTW_READ16(regs, ofs) \
|
|
bus_space_read_2((regs)->r_bt, (regs)->r_bh, (ofs))
|
|
|
|
#define RTW_READ(regs, ofs) \
|
|
bus_space_read_4((regs)->r_bt, (regs)->r_bh, (ofs))
|
|
|
|
#define RTW_WRITE8(regs, ofs, val) \
|
|
bus_space_write_1((regs)->r_bt, (regs)->r_bh, (ofs), (val))
|
|
|
|
#define RTW_WRITE16(regs, ofs, val) \
|
|
bus_space_write_2((regs)->r_bt, (regs)->r_bh, (ofs), (val))
|
|
|
|
#define RTW_WRITE(regs, ofs, val) \
|
|
bus_space_write_4((regs)->r_bt, (regs)->r_bh, (ofs), (val))
|
|
|
|
#define RTW_ISSET(regs, reg, mask) \
|
|
(RTW_READ((regs), (reg)) & (mask))
|
|
|
|
#define RTW_CLR(regs, reg, mask) \
|
|
RTW_WRITE((regs), (reg), RTW_READ((regs), (reg)) & ~(mask))
|
|
|
|
/* bus_space(9) lied? */
|
|
#ifndef BUS_SPACE_BARRIER_SYNC
|
|
#define BUS_SPACE_BARRIER_SYNC (BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
|
|
#endif
|
|
|
|
#ifndef BUS_SPACE_BARRIER_READ_BEFORE_READ
|
|
#define BUS_SPACE_BARRIER_READ_BEFORE_READ BUS_SPACE_BARRIER_READ
|
|
#endif
|
|
|
|
#ifndef BUS_SPACE_BARRIER_READ_BEFORE_WRITE
|
|
#define BUS_SPACE_BARRIER_READ_BEFORE_WRITE BUS_SPACE_BARRIER_READ
|
|
#endif
|
|
|
|
#ifndef BUS_SPACE_BARRIER_WRITE_BEFORE_READ
|
|
#define BUS_SPACE_BARRIER_WRITE_BEFORE_READ BUS_SPACE_BARRIER_WRITE
|
|
#endif
|
|
|
|
#ifndef BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE
|
|
#define BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE BUS_SPACE_BARRIER_WRITE
|
|
#endif
|
|
|
|
/*
|
|
* Bus barrier
|
|
*
|
|
* Complete outstanding read and/or write ops on [reg0, reg1]
|
|
* ([reg1, reg0]) before starting new ops on the same region. See
|
|
* acceptable bus_space_barrier(9) for the flag definitions.
|
|
*/
|
|
#define RTW_BARRIER(regs, reg0, reg1, flags) \
|
|
bus_space_barrier((regs)->r_bh, (regs)->r_bt, \
|
|
MIN(reg0, reg1), MAX(reg0, reg1) - MIN(reg0, reg1) + 4, flags)
|
|
|
|
/*
|
|
* Barrier convenience macros.
|
|
*/
|
|
/* sync */
|
|
#define RTW_SYNC(regs, reg0, reg1) \
|
|
RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_SYNC)
|
|
|
|
/* write-before-write */
|
|
#define RTW_WBW(regs, reg0, reg1) \
|
|
RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE)
|
|
|
|
/* write-before-read */
|
|
#define RTW_WBR(regs, reg0, reg1) \
|
|
RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_READ)
|
|
|
|
/* read-before-read */
|
|
#define RTW_RBR(regs, reg0, reg1) \
|
|
RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_READ)
|
|
|
|
/* read-before-read */
|
|
#define RTW_RBW(regs, reg0, reg1) \
|
|
RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_WRITE)
|
|
|
|
#define RTW_WBRW(regs, reg0, reg1) \
|
|
RTW_BARRIER(regs, reg0, reg1, \
|
|
BUS_SPACE_BARRIER_WRITE_BEFORE_READ | \
|
|
BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE)
|
|
|
|
/*
|
|
* Registers for RTL8180L's built-in baseband modem.
|
|
*/
|
|
#define RTW_BBP_SYS1 0x00
|
|
#define RTW_BBP_TXAGC 0x03 /* guess: transmit auto gain control */
|
|
#define RTW_BBP_LNADET 0x04 /* guess: low-noise amplifier activation
|
|
* threshold
|
|
*/
|
|
#define RTW_BBP_IFAGCINI 0x05 /* guess: intermediate frequency (IF)
|
|
* auto-gain control (AGC) initial value
|
|
*/
|
|
#define RTW_BBP_IFAGCLIMIT 0x06 /* guess: IF AGC maximum value */
|
|
#define RTW_BBP_IFAGCDET 0x07 /* guess: activation threshold for
|
|
* IF AGC loop
|
|
*/
|
|
|
|
#define RTW_BBP_ANTATTEN 0x10 /* guess: antenna & attenuation */
|
|
#define RTW_BBP_ANTATTEN_GCT_MAGIC 0xa3
|
|
#define RTW_BBP_ANTATTEN_PHILIPS_MAGIC 0x91
|
|
#define RTW_BBP_ANTATTEN_INTERSIL_MAGIC 0x92
|
|
#define RTW_BBP_ANTATTEN_RFMD_MAGIC 0x93
|
|
#define RTW_BBP_ANTATTEN_MAXIM_MAGIC 0xb3
|
|
#define RTW_BBP_ANTATTEN_DFLANTB 0x40
|
|
#define RTW_BBP_ANTATTEN_CHAN14 0x0c
|
|
|
|
#define RTW_BBP_TRL 0x11 /* guess: transmit/receive
|
|
* switch latency
|
|
*/
|
|
#define RTW_BBP_SYS2 0x12
|
|
#define RTW_BBP_SYS2_ANTDIV 0x80 /* enable antenna diversity */
|
|
#define RTW_BBP_SYS2_RATE_MASK __BITS(5,4) /* loopback rate?
|
|
* 0: 1Mbps
|
|
* 1: 2Mbps
|
|
* 2: 5.5Mbps
|
|
* 3: 11Mbps
|
|
*/
|
|
#define RTW_BBP_SYS3 0x13
|
|
/* carrier-sense threshold */
|
|
#define RTW_BBP_SYS3_CSTHRESH_MASK __BITS(0,3)
|
|
#define RTW_BBP_CHESTLIM 0x19 /* guess: channel energy-detect
|
|
* threshold
|
|
*/
|
|
#define RTW_BBP_CHSQLIM 0x1a /* guess: channel signal-quality
|
|
* threshold
|
|
*/
|