uwe f0757531d4 Only SH7750 and SH7750S require updates to memory-mapped data cache ... arrays to be performed while running on P2. Don't penalize other cpus that can do it from P1.		2008-03-16 19:17:53 +00:00
..
conf	defflag cache related options.	2008-03-15 22:48:58 +00:00
dev	Interrupt handling changes, in discussion since February:	2007-12-03 15:33:00 +00:00
include	Rewrite RUN_P2, RUN_P1 in asm. gcc4 is too happy to optimize away	2008-03-16 19:14:08 +00:00
sh3	Only SH7750 and SH7750S require updates to memory-mapped data cache	2008-03-16 19:17:53 +00:00
Makefile
Makefile.inc