441 lines
11 KiB
C
441 lines
11 KiB
C
/* $NetBSD: esp_mca.c,v 1.2 2001/12/04 20:47:58 jdolecek Exp $ */
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/*-
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* Copyright (c) 1997, 1998, 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Charles M. Hannum, Jason R. Thorpe of the Numerical Aerospace
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* Simulation Facility, NASA Ames Research Center and Jaromir Dolecek.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Driver for NCR 53c90, MCA version, with 86c01 DMA controller chip.
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*
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* Some of the information used to write this driver was taken
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* from Tymm Twillman <tymm@computer.org>'s Linux MCA NC53c90 driver,
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* in drivers/scsi/mca_53c9x.c
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*/
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/errno.h>
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#include <sys/ioctl.h>
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#include <sys/device.h>
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#include <sys/buf.h>
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#include <sys/proc.h>
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#include <sys/user.h>
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#include <sys/queue.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <dev/scsipi/scsi_message.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <dev/ic/ncr53c9xreg.h>
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#include <dev/ic/ncr53c9xvar.h>
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#include <dev/mca/espvar.h>
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#include <dev/mca/espreg.h>
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#include <dev/mca/mcavar.h>
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#include <dev/mca/mcareg.h>
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#include <dev/mca/mcadevs.h>
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#if 0
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#if defined(DEBUG) && !defined(NCR53C9X_DEBUG)
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#define NCR53C9X_DEBUG
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#endif
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#endif
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#ifdef NCR53C9X_DEBUG
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static int esp_mca_debug = 0;
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#define DPRINTF(x) if (esp_mca_debug) printf x;
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#else
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#define DPRINTF(x)
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#endif
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#define ESP_MCA_IOSIZE 0x20
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#define ESP_REG_OFFSET 0x10
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static void esp_mca_attach __P((struct device *, struct device *, void *));
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static int esp_mca_match __P((struct device *, struct cfdata *, void *));
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/* Linkup to the rest of the kernel */
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struct cfattach esp_mca_ca = {
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sizeof(struct esp_softc), esp_mca_match, esp_mca_attach
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};
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/*
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* Functions and the switch for the MI code.
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*/
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static u_char esp_read_reg __P((struct ncr53c9x_softc *, int));
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static void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char));
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static int esp_dma_isintr __P((struct ncr53c9x_softc *));
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static void esp_dma_reset __P((struct ncr53c9x_softc *));
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static int esp_dma_intr __P((struct ncr53c9x_softc *));
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static int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *,
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size_t *, int, size_t *));
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static void esp_dma_go __P((struct ncr53c9x_softc *));
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static void esp_dma_stop __P((struct ncr53c9x_softc *));
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static int esp_dma_isactive __P((struct ncr53c9x_softc *));
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static struct ncr53c9x_glue esp_glue = {
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esp_read_reg,
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esp_write_reg,
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esp_dma_isintr,
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esp_dma_reset,
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esp_dma_intr,
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esp_dma_setup,
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esp_dma_go,
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esp_dma_stop,
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esp_dma_isactive,
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NULL, /* gl_clear_latched_intr */
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};
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static int
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esp_mca_match(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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struct mca_attach_args *ma = aux;
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switch (ma->ma_id) {
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case MCA_PRODUCT_NCR53C90:
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return 1;
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}
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return 0;
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}
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static void
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esp_mca_attach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct mca_attach_args *ma = aux;
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struct esp_softc *esc = (void *)self;
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struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
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u_int16_t iobase;
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int scsi_id, irq, drq, error;
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bus_space_handle_t ioh;
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int pos2, pos3, pos5;
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static const u_int16_t ncrmca_iobase[] = {
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0, 0x240, 0x340, 0x400, 0x420, 0x3240, 0x8240, 0xa240
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};
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/*
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* NCR SCSI Adapter (ADF 7f4f)
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*
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* POS register 2: (adf pos0)
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*
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* 7 6 5 4 3 2 1 0
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* \_/ \___/ \__ enable: 0=adapter disabled, 1=adapter enabled
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* | \____ I/O base (32B): 001=0x240 010=0x340 011=0x400
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* | 100=0x420 101=0x3240 110=0x8240 111=0xa240
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* \__________ IRQ: 00=3 01=5 10=7 11=9
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*
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* POS register 3: (adf pos1)
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*
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* 7 6 5 4 3 2 1 0
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* 1 1 1 | \_____/
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* | \__ DMA level
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* \_________ Fairness: 1=enabled 0=disabled
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*
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* POS register 5: (adf pos3)
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*
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* 7 6 5 4 3 2 1 0
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* 1 | \___/
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* | \__ Static Ram: 0xC8000-0xC87FF + XX*0x4000
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* \___________ Host Adapter ID: 1=7 0=6
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*/
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pos2 = mca_conf_read(ma->ma_mc, ma->ma_slot, 2);
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pos3 = mca_conf_read(ma->ma_mc, ma->ma_slot, 3);
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pos5 = mca_conf_read(ma->ma_mc, ma->ma_slot, 5);
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iobase = ncrmca_iobase[(pos2 & 0x0e) >> 1];
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irq = 3 + 2*((pos2 & 0x30) >> 4);
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drq = (pos3 & 0x0f);
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scsi_id = 6 + ((pos5 & 0x20) ? 1 : 0);
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printf(" slot %d irq %d drq %d: NCR SCSI Adapter\n",
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ma->ma_slot + 1, irq, drq);
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/* Map the 86C01 registers */
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if (bus_space_map(ma->ma_iot, iobase, ESP_MCA_IOSIZE, 0, &ioh)) {
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printf("%s: can't map i/o space\n", sc->sc_dev.dv_xname);
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return;
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}
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esc->sc_iot = ma->ma_iot;
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esc->sc_ioh = ioh;
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/* Submap the 'esp' registers */
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if (bus_space_subregion(ma->ma_iot, ioh, ESP_REG_OFFSET,
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ESP_MCA_IOSIZE-ESP_REG_OFFSET, &esc->sc_esp_ioh)) {
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printf("%s: can't subregion i/o space\n", sc->sc_dev.dv_xname);
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return;
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}
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/* Setup DMA map */
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esc->sc_dmat = ma->ma_dmat;
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if ((error = mca_dmamap_create(esc->sc_dmat, MAXPHYS,
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BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW | MCABUS_DMA_IOPORT,
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&esc->sc_xfer, drq)) != 0){
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printf("%s: couldn't create DMA map - error %d\n",
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sc->sc_dev.dv_xname, error);
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return;
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}
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/* MI code glue */
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sc->sc_id = scsi_id;
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sc->sc_freq = 25; /* Mhz */
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sc->sc_glue = &esp_glue;
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sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; //| NCRCFG1_SLOW;
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/* No point setting sc_cfg[2345], they won't be used */
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sc->sc_rev = NCR_VARIANT_NCR53C90_86C01;
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sc->sc_minsync = 0;
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/* max 64KB DMA */
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sc->sc_maxxfer = 64 * 1024;
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/* Establish interrupt */
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esc->sc_ih = mca_intr_establish(ma->ma_mc, irq, IPL_BIO, ncr53c9x_intr,
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esc);
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if (esc->sc_ih == NULL) {
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printf("%s: couldn't establish interrupt\n",
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sc->sc_dev.dv_xname);
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return;
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}
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/*
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* Massage the 86C01 chip - setup MCA DMA controller for DMA via
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* the 86C01 register, and enable 86C01 interrupts.
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*/
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mca_dma_set_ioport(drq, iobase + N86C01_PIO);
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bus_space_write_1(esc->sc_iot, esc->sc_ioh, N86C01_MODE_ENABLE,
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bus_space_read_1(esc->sc_iot, esc->sc_ioh, N86C01_MODE_ENABLE)
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| N86C01_INTR_ENABLE);
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/*
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* Now try to attach all the sub-devices
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*/
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sc->sc_adapter.adapt_minphys = minphys;
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sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request;
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/* Do the common parts of attachment. */
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printf("%s", sc->sc_dev.dv_xname);
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ncr53c9x_attach(sc);
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}
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/*
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* Glue functions.
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*/
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static u_char
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esp_read_reg(sc, reg)
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struct ncr53c9x_softc *sc;
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int reg;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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return (bus_space_read_1(esc->sc_iot, esc->sc_esp_ioh, reg));
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}
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static void
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esp_write_reg(sc, reg, val)
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struct ncr53c9x_softc *sc;
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int reg;
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u_char val;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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bus_space_write_1(esc->sc_iot, esc->sc_esp_ioh, reg, val);
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}
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static int
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esp_dma_isintr(sc)
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struct ncr53c9x_softc *sc;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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DPRINTF(("[esp_dma_isintr] "));
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return (bus_space_read_1(esc->sc_iot, esc->sc_ioh,
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N86C01_STATUS) & N86C01_IRQ_PEND);
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}
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static void
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esp_dma_reset(sc)
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struct ncr53c9x_softc *sc;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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DPRINTF(("[esp_dma_reset] "));
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if (esc->sc_flags & ESP_XFER_LOADED) {
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bus_dmamap_unload(esc->sc_dmat, esc->sc_xfer);
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esc->sc_flags &= ~ESP_XFER_LOADED;
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}
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if (esc->sc_flags & ESP_XFER_ACTIVE) {
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esc->sc_flags &= ~ESP_XFER_ACTIVE;
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mca_disk_unbusy();
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}
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}
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static int
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esp_dma_intr(sc)
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struct ncr53c9x_softc *sc;
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{
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struct esp_softc *esc = (struct esp_softc *) sc;
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DPRINTF(("[esp_dma_intr] "));
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if ((esc->sc_flags & ESP_XFER_ACTIVE) == 0) {
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printf("%s: dma_intr--inactive DMA\n", sc->sc_dev.dv_xname);
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return (-1);
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}
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if ((sc->sc_espintr & NCRINTR_BS) == 0) {
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esc->sc_flags &= ~ESP_XFER_ACTIVE;
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mca_disk_unbusy();
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return (0);
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}
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sc->sc_espstat |= NCRSTAT_TC; /* XXX */
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if ((sc->sc_espstat & NCRSTAT_TC) == 0) {
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printf("%s: DMA not complete?\n", sc->sc_dev.dv_xname);
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return (1);
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}
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bus_dmamap_sync(esc->sc_dmat, esc->sc_xfer, 0,
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*esc->sc_xfer_len,
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(esc->sc_flags & ESP_XFER_READ)
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? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
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bus_dmamap_unload(esc->sc_dmat, esc->sc_xfer);
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esc->sc_flags &= ~ESP_XFER_LOADED;
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*esc->sc_xfer_addr += *esc->sc_xfer_len;
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*esc->sc_xfer_len = 0;
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esc->sc_flags &= ~ESP_XFER_ACTIVE;
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mca_disk_unbusy();
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return (0);
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}
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/*
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* Setup DMA transfer.
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*/
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static int
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esp_dma_setup(sc, addr, len, datain, dmasize)
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struct ncr53c9x_softc *sc;
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caddr_t *addr;
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size_t *len;
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int datain;
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size_t *dmasize;
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{
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struct esp_softc *esc = (struct esp_softc *) sc;
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int error;
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int fl;
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DPRINTF(("[esp_dma_setup] "));
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if (esc->sc_flags & ESP_XFER_LOADED) {
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printf("%s: esp_dma_setup: unloading leaked xfer\n",
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sc->sc_dev.dv_xname);
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bus_dmamap_unload(esc->sc_dmat, esc->sc_xfer);
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esc->sc_flags &= ~ESP_XFER_LOADED;
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}
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/* Load the buffer for DMA transfer. */
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fl = (datain) ? BUS_DMA_READ : BUS_DMA_WRITE;
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if ((error = bus_dmamap_load(esc->sc_dmat, esc->sc_xfer, *addr,
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*len, NULL, BUS_DMA_STREAMING|fl))) {
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printf("%s: esp_dma_setup: unable to load DMA buffer - error %d\n",
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sc->sc_dev.dv_xname, error);
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return (error);
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}
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bus_dmamap_sync(esc->sc_dmat, esc->sc_xfer, 0,
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*len, (datain) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
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esc->sc_flags |= ESP_XFER_LOADED | (datain ? ESP_XFER_READ : 0);
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esc->sc_xfer_addr = addr;
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esc->sc_xfer_len = len;
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return (0);
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}
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static void
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esp_dma_go(sc)
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struct ncr53c9x_softc *sc;
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{
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struct esp_softc *esc = (struct esp_softc *) sc;
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DPRINTF(("[esp_dma_go] "));
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esc->sc_flags |= ESP_XFER_ACTIVE;
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mca_disk_busy();
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}
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static void
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esp_dma_stop(sc)
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struct ncr53c9x_softc *sc;
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{
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DPRINTF(("[esp_dma_stop] "));
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panic("%s: stop not yet implemented", sc->sc_dev.dv_xname);
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}
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static int
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esp_dma_isactive(sc)
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struct ncr53c9x_softc *sc;
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{
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struct esp_softc *esc = (struct esp_softc *) sc;
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DPRINTF(("[esp_dma_isactive] "));
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return (esc->sc_flags & ESP_XFER_ACTIVE);
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}
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