79d9ef08e7
Reported by Rocky Hotas. - On ASUS M2N-MX SE Plus (NVIDIA MCP61 with Attansic L2 rev. 1), changing debug port 0x29's value makes the next PHY read fail with error. Read any register to ignore this problem if the PHY is Attansic L2 revision 1. I don't know if this problem is from L2 rev. 1 itself or from the combination because I have only one machine which has L2 rev. "1". At least, ASUS eee pc 900 (Attansic L2 rev. "2") has no this problem. - Add comment. AR8021 document has no description about the power saving control register(debug port 0x29). - Add comment. AR8031 document says the lower 14 bits are reserved and the default value is 0x36d0. Shouldn't we clear those bits? - I have no document neither L1(F1) nor L2(F2), so I don't know whether the debug port access is correct or not. Tested with the following machines: - ASUS P5B SE, L1 rev. 5, age(4) - ASUS K50IJ, L1 rev. 9, ale(4) - ASUS eee pc 900, L2 rev. 2, lii(4) - ASUS M2N-MX SE Plus, L2 rev. 1, nfe(4) - Intel DP55WB, 82578(AR8021 rev. 2), wm(4) - Dell inspiron 14z, AR0835 rev. 9, alc(4)
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