185 lines
6.2 KiB
C
185 lines
6.2 KiB
C
/* $NetBSD: cache.h,v 1.2 2002/02/17 20:58:02 uch Exp $ */
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/*-
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* Copyright (c) 2002 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Cache configurations.
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*
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* SH3 I/D unified virtual-index physical-tag cache.
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* SH4 I/D separated virtual-index physical-tag cache.
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*
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*
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* size line-size entry way
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* SH7708 4/8K 16B 128 2/4 P0, P2, U0 write-through/back selectable
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* P1 write-through
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* SH7709 4/8K 16B 128 2/4 write-through/back selectable
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* SH7709A 16K 16B 256 4 write-through/back selectable
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*
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* SH7750 I$ D$ line-size entry way
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* 8K 8/16K 32B 256 1 write-through/back selectable
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*
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*
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* Cache operations.
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*
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* There are some rules that must be followed:
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*
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* I-cache Synch (all or range):
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* The goal is to synchronize the instruction stream,
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* so you may need to write-back dirty data cache
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* blocks first. If a range is requested, and you
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* can't synchronize just a range, you have to hit
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* the whole thing.
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*
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* D-cache Write-back Invalidate range:
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* If you can't WB-Inv a range, you must WB-Inv the
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* entire D-cache.
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*
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* D-cache Invalidate:
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* If you can't Inv the D-cache without doing a
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* Write-back, YOU MUST PANIC. This is to catch
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* errors in calling code. Callers must be aware
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* of this scenario, and must handle it appropriately
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* (consider the bus_dma(9) operations).
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*
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* D-cache Write-back:
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* If you can't Write-back without doing an invalidate,
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* that's fine. Then treat this as a WB-Inv. Skipping
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* the invalidate is merely an optimization.
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*
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* All operations:
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* Valid virtual addresses must be passed to the
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* cache operation.
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*
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*
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* sh_icache_sync_all Synchronize I-cache
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*
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* sh_icache_sync_range Synchronize I-cache range
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*
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* sh_icache_sync_range_index (index ops)
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*
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* sh_dcache_wbinv_all Write-back Invalidate D-cache
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*
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* sh_dcache_wbinv_range Write-back Invalidate D-cache range
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*
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* sh_dcache_wbinv_range_index (index ops)
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*
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* sh_dcache_inv_range Invalidate D-cache range
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*
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* sh_dcache_wb_range Write-back D-cache range
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*
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* If I/D unified cache (SH3), I-cache ops are writeback invalidate
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* operation.
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* If write-through mode, sh_dcache_wb_range is no-operation.
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*
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*/
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#ifndef _SH3_CACHE_H_
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#define _SH3_CACHE_H_
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#ifdef _KERNEL
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#define COMPAT_OLD_CACHE_FLUSH //XXX
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#ifdef COMPAT_OLD_CACHE_FLUSH
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#define cacheflush() sh_dcache_wbinv_all()
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#endif /* COMPAT_OLD_CACHE_FLUSH */
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struct sh_cache_ops {
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void (*_icache_sync_all)(void);
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void (*_icache_sync_range)(vaddr_t, vsize_t);
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void (*_icache_sync_range_index)(vaddr_t, vsize_t);
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void (*_dcache_wbinv_all)(void);
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void (*_dcache_wbinv_range)(vaddr_t, vsize_t);
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void (*_dcache_wbinv_range_index)(vaddr_t, vsize_t);
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void (*_dcache_inv_range)(vaddr_t, vsize_t);
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void (*_dcache_wb_range)(vaddr_t, vsize_t);
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};
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/* Cache configurations */
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#define sh_cache_enable_unified sh_cache_enable_icache
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extern int sh_cache_enable_icache;
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extern int sh_cache_enable_dcache;
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extern int sh_cache_write_through;
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extern int sh_cache_write_through_p0_u0_p3;
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extern int sh_cache_write_through_p1;
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extern int sh_cache_ways;
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extern int sh_cache_unified;
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#define sh_cache_size_unified sh_cache_size_icache
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extern int sh_cache_size_icache;
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extern int sh_cache_size_dcache;
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extern int sh_cache_line_size;
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/* for n-way set associative cache */
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extern int sh_cache_way_size;
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extern int sh_cache_way_shift;
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extern int sh_cache_entry_mask;
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/* Special mode */
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extern int sh_cache_ram_mode;
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extern int sh_cache_index_mode_icache;
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extern int sh_cache_index_mode_dcache;
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extern struct sh_cache_ops sh_cache_ops;
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#define sh_icache_sync_all() \
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(*sh_cache_ops._icache_sync_all)()
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#define sh_icache_sync_range(v, s) \
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(*sh_cache_ops._icache_sync_range)((v), (s))
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#define sh_icache_sync_range_index(v, s) \
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(*sh_cache_ops._icache_sync_range_index)((v), (s))
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#define sh_dcache_wbinv_all() \
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(*sh_cache_ops._dcache_wbinv_all)()
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#define sh_dcache_wbinv_range(v, s) \
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(*sh_cache_ops._dcache_wbinv_range)((v), (s))
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#define sh_dcache_wbinv_range_index(v, s) \
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(*sh_cache_ops._dcache_wbinv_range_index)((v), (s))
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#define sh_dcache_inv_range(v, s) \
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(*sh_cache_ops._dcache_inv_range)((v), (s))
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#define sh_dcache_wb_range(v, s) \
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(*sh_cache_ops._dcache_wb_range)((v), (s))
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void sh_cache_init(void);
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void sh_cache_information(void);
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#endif /* _KERNEL */
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#endif /* _SH3_CACHE_H_ */
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