123 lines
4.7 KiB
C
123 lines
4.7 KiB
C
/* $NetBSD: ihphyreg.h,v 1.3 2024/02/09 22:08:35 andvar Exp $ */
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/*-
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* Copyright (c) 2010 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_MII_IHPHYREG_H_
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#define _DEV_MII_IHPHYREG_H_
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#include <dev/mii/inbmphyreg.h>
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/*
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* Intel 82577LM registers.
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*/
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/* PHY Control Register 2 */
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#define IHPHY_MII_ECR2 BME1000_REG(0, 18)
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/* Loopback Control Register */
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#define IHPHY_MII_LCR BME1000_REG(0, 19)
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/* RX Error Counter Register */
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#define IHPHY_MII_RXERR BME1000_REG(0, 20)
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/* Management Interface Register */
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#define IHPHY_MII_MIR BME1000_REG(0, 21)
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/* PHY Configuration Register */
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#define IHPHY_MII_CFG BME1000_REG(0, 22)
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#define IHPHY_CFG_TX_CRS 0x8000 /* CRS transmit enable */
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#define IHPHY_CFG_FIFO_DEPTH 0x3000 /* Transmit FIFO depth*/
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#define IHPHY_CFG_DOWN_SHIFT 0x0C00 /* Automatic speed downshift mode */
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#define IHPHY_CFG_ALT_PAGE 0x0080 /* Alternate next page */
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#define IHPHY_CFG_GRP_MDIO 0x0040 /* Group MDIO mode enable */
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#define IHPHY_CFG_TX_CLOCK 0x0020 /* Transmit clock enable */
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/* PHY Control Register */
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#define IHPHY_MII_ECR BME1000_REG(0, 23)
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#define IHPHY_ECR_LNK_EN 0x2000 /* Link enable */
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#define IHPHY_ECR_DOWN_SHIFT 0x1C00 /* Automatic speed downshift attempts */
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#define IHPHY_ECR_LNK_PARTNER 0x0080 /* Link Partner Detected */
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#define IHPHY_ECR_JABBER 0x0040 /* Jabber (10BASE-T) */
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#define IHPHY_ECR_SQE 0x0020 /* Heartbeat (10BASE-T) */
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#define IHPHY_ECR_TP_LOOPBACK 0x0010 /* TP loopback (10BASE-T) */
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#define IHPHY_ECR_PRE_LENGTH 0x000C /* Preamble length (10BASE-T) */
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/* Interrupt Mask Register */
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#define IHPHY_MII_IMR BME1000_REG(0, 24)
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/* Interrupt Status Register */
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#define IHPHY_MII_ISR BME1000_REG(0, 25)
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/* PHY Status Register */
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#define IHPHY_MII_ESR BME1000_REG(0, 26)
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#define IHPHY_ESR_STANDBY 0x8000 /* PHY in standby */
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#define IHPHY_ESR_ANEG_FAULT 0x6000 /* Autonegotiation fault status */
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#define IHPHY_ESR_ANEG_STAT 0x1000 /* Autonegotiation status */
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#define IHPHY_ESR_PAIR_SWAP 0x0800 /* Pair swap on pairs A and B */
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#define IHPHY_ESR_POLARITY 0x0400 /* Polarity status */
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#define IHPHY_ESR_SPEED 0x0300 /* Speed status */
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#define IHPHY_ESR_DUPLEX 0x0080 /* Duplex status */
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#define IHPHY_ESR_LINK 0x0040 /* Link status */
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#define IHPHY_ESR_TRANSMIT 0x0020 /* Transmit status */
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#define IHPHY_ESR_RECEIVE 0x0010 /* Receive status */
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#define IHPHY_ESR_COLLISION 0x0008 /* Collision status */
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#define IHPHY_ESR_ANEG_BOTH 0x0004 /* Autonegotiation enabled for both */
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#define IHPHY_ESR_PAUSE 0x0002 /* Link partner has PAUSE */
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#define IHPHY_ESR_ASYM_PAUSE 0x0001 /* Link partner has asymmetric PAUSE */
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#define IHPHY_SPEED_10 0x0000
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#define IHPHY_SPEED_100 0x0100
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#define IHPHY_SPEED_1000 0x0200
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/* LED Control Register 1 */
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#define IHPHY_MII_LED1 BME1000_REG(0, 27)
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/* LED Control Register 2 */
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#define IHPHY_MII_LED2 BME1000_REG(0, 28)
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/* LED Control Register 3 */
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#define IHPHY_MII_LED3 BME1000_REG(0, 29)
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/* Diagnostics Control Register */
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#define IHPHY_MII_DCR BME1000_REG(0, 30)
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/* Diagnostics Status Register */
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#define IHPHY_MII_DSR BME1000_REG(0, 31)
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/*
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* XXX I21[789] documents say that the SMBus Address register is at
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* PHY address 01, Page 0 (not 768), Register 26.
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*/
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#define HV_SMB_ADDR BME1000_REG(768, 26)
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#define HV_SMB_ADDR_ADDR 0x007f
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#define HV_SMB_ADDR_VALID (1 << 7)
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#define HV_SMB_ADDR_FREQ_LOW (1 << 8)
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#define HV_SMB_ADDR_PEC_EN (1 << 9)
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#define HV_SMB_ADDR_FREQ_HIGH (1 << 12)
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#endif /* _DEV_IHPHY_MIIREG_H_ */
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