97 lines
3.1 KiB
C
97 lines
3.1 KiB
C
/* $NetBSD: intr.h,v 1.22 2008/01/04 22:03:25 ad Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Jonathan Stone for
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* the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _HPCMIPS_INTR_H_
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#define _HPCMIPS_INTR_H_
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#define IPL_NONE 0 /* disable only this interrupt */
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#define IPL_SOFTCLOCK 1 /* clock software interrupts (SI 0) */
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#define IPL_SOFTBIO 1 /* bio software interrupts (SI 0) */
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#define IPL_SOFTNET 2 /* network software interrupts (SI 1) */
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#define IPL_SOFTSERIAL 2 /* serial software interrupts (SI 1) */
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#define IPL_VM 3
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#define IPL_SCHED 4
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#define IPL_HIGH 4 /* disable all interrupts */
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#define _IPL_N 5
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#define _IPL_SI0_FIRST IPL_SOFTCLOCK
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#define _IPL_SI0_LAST IPL_SOFTBIO
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#define _IPL_SI1_FIRST IPL_SOFTNET
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#define _IPL_SI1_LAST IPL_SOFTSERIAL
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/* Interrupt sharing types. */
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#define IST_UNUSABLE -1 /* interrupt cannot be used */
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#define IST_NONE 0 /* none */
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#define IST_PULSE 1 /* pulsed */
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#define IST_EDGE 2 /* edge-triggered */
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#define IST_LEVEL 3 /* level-triggered */
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#ifdef _KERNEL
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#ifndef _LOCORE
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#include <mips/cpuregs.h>
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#include <mips/locore.h>
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extern const u_int32_t *ipl_sr_bits;
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void intr_init(void);
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#define spl0() (void) _spllower(0)
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#define splx(s) (void) _splset(s)
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typedef int ipl_t;
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typedef struct {
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ipl_t _sr;
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} ipl_cookie_t;
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static inline ipl_cookie_t
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makeiplcookie(ipl_t ipl)
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{
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return (ipl_cookie_t){._sr = ipl_sr_bits[ipl]};
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}
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static inline int
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splraiseipl(ipl_cookie_t icookie)
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{
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return _splraise(icookie._sr);
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}
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#include <sys/spl.h>
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#endif /* !_LOCORE */
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#endif /* _KERNEL */
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#endif /* !_HPCMIPS_INTR_H_ */
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